Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam

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Georgia Institute of Technology School of Electrical and Computer Engineering Midterm Exam ECE-3400 Fall 2013 Tue, September 24, 2013 Duration: 80min First name Solutions Last name Solutions ID

1 Georgia Institute of Technology School of Electrical and Computer Engineering Midterm Exam ECE-3400 Fall 2013 Tue, September 24, 2013 Duration: 80min First name Solutions Last name Solutions ID number This is a close-book, close-note exam. For this exam no computer, tablet, smartphone, or programmable calculator is permitted. You can bring one sheet of equations that you have prepared ahead of the exam. Show your work and reasoning for partial credits. Remember to write you name on each page. Please consider the following honor pledge. I have neither given nor received any unauthorized assistance on this exam. Signature KP n = K n KP p = K p V THP is the absolute value of the PMOS threshold voltage. U T = kt/q = 25 T = 300 K k = J/K q = C 1

2 1. Respond to the following questions very briefly (only a few sentences): [30] (a) Why a reversed-based diode shows capacitive effects? What is the name of that capacitance? (b) If the reverse bias across the diode increases how does the capacitance in (a) change? Why? (c) Why a forward-biased diode shows capacitive effects? What is the name of that capacitance? (d) If the current in the forward-based diode increases, how does the capacitance in (c) change? Why? (e) Draw the schematic and cross-section of a CMOS inverter on a P-type silicon substrate. Make sure to including the body contacts in both diagrams. (f) On the cross-section of the inverter in (e), indicate 2 MOSFETs, 5 diodes, 2 BJTs, and 7 capacitors. (g) What is the Early effect? How is it considered in the mathematical model for the collector current of a BJT that is biased in the forward-active region. (h) If we need a digital potentiometer in a mixed-mode CMOS ASIC, what is the best way to implement it? (i) Draw a simple block diagram for the digital potentiometer in (h), controlled by a 4-bit digital input. (j) If the two BJT transistors in the following figure have similar impurity levels, which one can handle a larger voltage in the shown polarity before it breaks down? Why? 2

3 (a) Changes in reverse voltage lead to changes in the width and stationary charge in the depletion region, resulting in a capacitive effect. This is called reverse-bias capacitance or junction capacitance. (b) The reverse-bias capacitance decreases because larger reverse bias increases the width of the depletion region, d, and C = ε r ε 0 A/d. (c) In forward bias operation, additional charge is stored in the neutral region near edges of space charge region due to diffusion of the minority carriers. This is called forward-bias capacitance or diffusion capacitance. (d) The forward bias capacitance increases. Additional diffuses charge, associated with forward region of operation, is proportional to forward current and becomes larger at higher current. (e) (f) (g) In a BJT, the collector current is affected by V CE, and increases with higher V CE, in the forward active region due to narrower base region. This is called the Early effect, and often 3

4 considered as a resistance between the collector and the emitter in the BJT model. In the collector current equation, the term on the far right represents the Early effect: (h) Use a MOSFET biased in the triode-region as a voltage-controlled resistor and adjust the gate-source voltage to change its resistance. (i) (j) The left figure has a larger breakdown voltage because of the asymmetric doping levels in the emitter and collector regions. The breakdown voltage is inversely proportional to the doping density. Therefore, the CB junction which has a lower doping level than the BE junction shows a higher breakdown voltage. 4

5 2. The following circuit has been implemented in a 1 µm CMOS process, which specifications are given in the table on the first page (V CC = 5 V, I S = 1pA). You can ignore channel length modulation. [40] (a) Indicate source, gate, and drain terminals for each MOSFET. Add the body terminal to each MOSFET on the schematic and connect it to the most suitable voltage in the circuit. (b) If the diodes are all identical with saturation current of I S, the drain current in M1 is I D1, and the drain current in M2 is I D2, find a parametric expression for the voltage across each diode. (c) Using the voltages in (b), find a parametric expression for Vout with respect to I D1 and I D2, assuming that the gain of the differential amplifier is A. (d) If the temperature, T (in K) in this circuit increases by 25%, what would be the % change in Vout and in what direction? (e) If the size of M1 is (W/L) 1 = 10 and the size of M2 is (W/L) 2 = 50, find the MOSFET bias voltage, Vp, such that I D1 = 200 µa. What would be I D2 in this condition? (f) Considering the drain currents in (e), find Vout at room temperature (300 K) if A = 10. What is Vout at 250 K? (g) What would be a practical application for the following circuit? 5

6 (a) M1 and M2 are PMOS transistors. Therefore, top terminals are sources, middle terminals are gates, and bottom terminals are drains. Body terminals of M1 and M2 should be connected to the highest voltage of the circuit, which is V CC. (b) = +1 = +1 Since we have 5 diodes in parallel, I S is 5 times larger. (c) = = = =. Since V SG1 = V SG2, I D1 /I D2 = W 1 /W 2. The two PMOSs form a current mirror. (d) =. Therefore, when the temperature increases by 25%, V out also increases by 25%. (e) Assume that M1 and M2 are in the saturation region. = 200 = 40 / =1.9 =5 =3.1 =5 =1 Assuming n = 1, =0.478, =0.478 V D1 and V D2 values confirm that M1 and M2 are in the saturation region. (f) = =10 =10 1 =0 (g) According to (c), V out is proportional to T. Therefore, this circuit can be considered to be a temperature sensor. This type of circuit is also known as Proportional To Absolute Temperature (PTAT) circuit. 6

3. The following circuit, consider the OpAmp to be ideal (an ideal OpAmp has an infinite gain, resulting in the same potential at its input terminals if it has a negative feedback).

7 3. The following circuit, consider the OpAmp to be ideal (an ideal OpAmp has an infinite gain, resulting in the same potential at its input terminals if it has a negative feedback). For the BJT, assume β F = 40. [30] (a) What is the current in the Zener diode? (b) What is the output voltage? (c) What are the values of the emitter current and the total current supplied by the 15 V supply? (d) What is the BJT region of operation and Q-point (I C, V EC )? (e) What is the OpAmp output voltage? (f) If the supply voltage increases from 15 V to 20 V, what would be the new output voltage? (g) If the supply voltage drops from 15 V to 12 V, what would be the new output voltage? (h) What would be a practical application for the following circuit? 7

8 (a) = = =122 (b) In the ideal OpAmp with negative feedback, the positive and negative input terminals have the same potentials, which is 5V in this case. = 5 =10 (c) = =106 = =109 = + = (d) Forward-active region. Q (I C, V EC ) = Q (106 ma, 5 V) (e) = +1 =25 +1 =635 OpAmp output voltage = = V (f) 10V (g) 10V (h) A voltage regulator, which generates constant supply voltage (V o ) from higher variable voltage source (12~20V in this case). 8

I E I C since I B is very small

I E I C since I B is very small Figure 2: Symbols and nomenclature of a (a) npn and (b) pnp transistor. The BJT consists of three regions, emitter, base, and collector. The emitter and collector are usually of one type of doping, while