1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1

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1 Contents 1 FUNDAMENTAL CONCEPTS What is Noise Coupling Resistance Resistivity and Resistance Wire Resistance Sheet Resistance Skin Effect Resistance of Semiconductors Resistive Coupling Resistive Coupling in Lightly Doped Substrates Resistive Coupling in Heavily Doped Substrates Resistive Coupling Through Voltage Drops Inductance Electric Current Flowing Through a Wire Conductive Wire Encircled by Magnetic Field Time Varying Current Flowing Through a Wire Self-Inductance of a Straight Wire Segment Inductive Coupling 19 v

2 vi Contents Mutual Inductance Total Inductance Loop Inductance Loop Mutual Inductance Capacitance Parallel Plate Capacitor Semiconductor Junction Capacitance Capacitive Coupling Wire to Wire Capacitive Coupling Decoupling Capacitors 32 2 INTEGRATED CIRCUITS FABRICATION Introduction Integrated Circuits Fabrication Technology Wafer Manufacturing Device Manufacturing Bipolar Process CMOS Process BiCMOS Process Silicon on Insulator (SOI) Process Packaging Technology Wire Bonding Package Tape Automated Bonding Package Flip-Chip Package Printed Circuit Boards Technology Power Distribution Power Distribution Model Decoupling Capacitors Example of a Power Distribution Model 73 3 MECHANISMS OF NOISE GENERATION Introduction Substrate Noise Generation NPN Transistor in Common-Emitter Configuration NPN Transistor in Cascode Configuration NPN Transistor in Emitter-Follower Configuration 80

3 Contents vii NPN Transistor in Common-Base Configuration PNP Transistor in Common-Emitter Configuration PNP Transistor in Common-Base Configuration PNP Transistor in Cascode Configuration PNP Transistor in Emitter-Follower Configuration NMOS Transistor in Common-Source Configuration Impact Ionization NMOS Transistor in Cascode Configuration NMOS Transistor in Source-Follower Configuration NMOS Transistor in Common-Gate Configuration PMOS Transistor in Common-Source Configuration PMOS Transistor in Cascode Configuration PMOS Transistor in Source-Follower Configuration PMOS Transistor in Common-Gate Configuration Schottky Diodes ESD Protection Structures Resistors Capacitors Inductors Noise Generation Through Bias Contacts Power Supply Noise Generation Transient Supply Currents Power Supply Noise Coupling into the Substrate Power Supply Noise Coupling into the Package and PCB Power Distribution Resonance MECHANISMS OF NOISE PROPAGATION Introduction Propagation Through Chip Substrate Propagation Through Lightly Doped Substrates Propagation Through Heavily Doped Substrates Propagation Through Silicon-On-Insulator (SOI) Substrates Propagation Through Power Distribution Propagation Through Crosstalk MECHANISMS OF NOISE RECEPTION Introduction Noise Reception Through Substrate and N-well Contacts 147

4 viii Contents Noise Reception in Standard CMOS Processes Noise Reception in Triple Well CMOS Processes Noise Reception in SOI CMOS Processes Noise Reception in Silicon Bipolar Processes Noise Reception in Bipolar Transistors Noise Reception in NPN Transistors Noise Reception in PNP Transistors Noise Reception in MOS Transistors Noise Reception in NMOS Transistors Noise Reception in PMOS Transistors Noise Reception in Resistors Noise Reception in Base Resistors Noise Reception in Emitter Resistors Noise Reception in Polysilicon Resistors Noise Reception in Capacitors Noise Reception in Diffusion Capacitors Noise Reception in MOS Capacitors Noise Coupling Effects on Latch-up NOISE COUPLING MEASUREMENT Introduction Requirements for Making Accurate Measurements P+ Diffusion Contacts and Sense Lines Backgate Modulation Sensors On Chip Digitizing Sensors Differential Amplifiers DC Coupled Substrate and Power Supply Differential Sensors On Chip Sampler Comparison of the Measurement Techniques 196

5 Contents ix 7 NOISE COUPLING SUPPRESSION Introduction Suppression of Noise Generation Differential CMOS Logic Single Ended Current Steering CMOS Current Balanced CMOS Supply Current Shaping Power Distribution Impedance Suppresion of Noise Propagation Using Lightly Doped Substrates Instead of Heavily Doped Buried Substrate Shields: Faraday Shield Buried Substrate Shields: Dielectric Shield (SOI process) Buried Substrate Shields: Junction Shield Shunting Guard Rings High Resistance Guard Rings Active Guard Rings Suppression of Noise Reception Differential Versus Single Ended Circuits Shunting Through Substrate Contacts Circuit Level Compensation Design Example 1: Circuit Level Compensation for Substrate Noise Coupling in Common-Source NMOS Amplifier Architecture and Functionality Experimental Results Design Example 2: Circuit Level Compensation for Substrate Noise Coupling in NMOS Active Loads Architecture and Functionality Experimental Results NOISE COUPLING SIMULATION Introduction Using Software Simulation Tools Overview of Noise Coupling Simulation Post-Layout Extraction and Simulation Pre-Layout Extraction and Simulation Early Estimation in the Architectural Stage of the Design 243

6 x Contents 8.3 Early Prediction of Noise Coupling Modeling Requirements Modeling Assumptions Methodology Estimation of the Digital Switching Noise Two-Dimensional Analog Mesh Alternate One-Dimensional Analog Mesh Digital Circuits, Package, and PCB Power Distribution Example of Early Prediction of Noise Coupling Model Construction Simulation Results and Correlation with Measurements 260