Source/Drain Parasitic Resistance Role and Electric Coupling Effect in Sub 50 nm MOSFET Design

Transcription

1 Source/Drain Parasitic Resistance Role and Electric Coupling Effect in Sub 50 nm MOSFET Design 9/25/2002 Jun Yuan, Peter M. Zeitzoff*, and Jason C.S. Woo Department of Electrical Engineering University of California, Los Angeles * SEMATECH, Austin, TX

2 Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions

3 Introduction MOSFET device performance is determined by carrier transportation, Source/Drain (S/D) electrostatic coupling, and parasitic resistance/capacitance effects Critical parameters for digital: I on / I off, DIBL, C*V/I MOSFET is driven into nanoscale regime 2 Carrier transportation is enhanced velocity overshoot 2 Worse SCE increased S/D electrostatic coupling effect Scaled down S/D junction depth S/D series resistance limitation

4 Introduction (cont) Reduce gate oxide thickness to enhance gate controllability gate tunneling limitation Increase substrate doping to reduce S/D electric coupling Carrier mobility, B-B tunneling and junction capacitance 2 R con / R c h is increased L g & T ox, contact area look for new material to reduce schottky barrier height (Φ B ) The purpose of this work is to study parasitic resistance role and S/D electric coupling effect in 45nm NMOS design, thus provide guideline for further scaling down of conventional bulk device

5 Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions

6 Simulated Device Structure (NMOS) contact Source POLY contact Drain L gate = 45nm L m = 30nm T gate,eq = 0.8nm K gate = 25 SDE offset region X je = 15nm X jc = 45nm Si substrate n - = 1~5x10 19 /cm 3 n + = 3x10 20 /cm 3 Abrupt junction is defined since hot carrier effect is not an issue SILVACO tool is used with energy balance model

7 Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions

8 S/D Extension Doping Effect Ion (µa/µm) I on,offset=0nm 300 I on,offset=7.5nm DIBL,offset=0nm 250 DIBL,offset=7.5nm DIBL (mv/v) ρ c = 1.2x10-7 Ω/µm 2 V dd =0.8 V I off =10 na/µm Extension doping concentration (cm -3, log) SCE is very sensitive to SDE doping (1x10 19 cm -3 ~1x10 20 cm -3 ) SDE doping in nonzero offset region is critical to series resistance

9 S/D Extension Offset Length Effect I on (µa/µm) Ion,SDE=5x10 19 cm -3 Ion,SDE=1x10 19 cm -3 DIBL,SDE=5x10 19 cm -3 DIBL,SDE=1x10 19 cm DIBl (mv/v) Normalied C*V/I N ext =5x10 19 cm -3 N ext =1x10 19 cm Extension offset length (nm) Extension offset length (nm) S/D series resistance is increased with SDE offset length increment DIBL can be decoupled from deep S/D region with large spacer design Device with low SDE doping but zero offset length design can improve Ion, DIBL and C*V/I

10 SDE-to-Gate Overlap Depth/Length Effect Ion,N ext =1x10 19 cm -3 Ion,N ext =5x10 19 cm I off =10nA/µm I on (µa/µm) I off =10nA/µm DIBL,N ext =1x10 19 cm -3 DIBL,N ext =5x10 19 cm Extension junction depth (Α) DIBL (mv/v) DIBL (mv/v) DIBL, doping=1x10 19 cm -3 DIBL, doping=5x10 19 cm -3 I on, doping=1x10 19 cm -3 I on, doping=5x10 19 cm SDE-to-Gate overlap length (A) Ion (µa/µm) Drive current is independent of SDE-togate overlap depth/length due to trade-off between V th and overlap resistance SDE-to-gate overlap can be eliminated to reduce SCE and overlap capacitance Source POLY ~ ~

11 Zero & Nonzero Gate-to-SDE overlap Device Performance Comparison (1) Drain current (µa/µm) with ext. overlap without ext. overlap Lg=45nm Drain current (µa/µm) with ext. overlap without ext. overlap Lg=500nm leakage current (A/µm) Leakage current (A/µm) Long channel: device with overlap has higher current drive due to smaller effective channel length, I on L eff -1 Short channel: Similar I on /I off performance due to velocity saturation and SCE limitation

12 Zero & Nonzero Gate-to-SDE Overlap Device Performance Comparison (2) 1.05 normalized C*V/I Lg=45nm with ext. overlap without ext. overlap leakage current (A/µm) normalized C*V/I Lg=500nm with ext. overlap without ext. overlap leakage current (A/µm) Long channel: SDE-to-Gate overlap improves device intrinsic speed due to enhanced drive current Short channel: SDE-to-Gate overlap degrades device speed due to increased overlap capacitance

13 Deep S/D Junction Depth Effect DIBL (mv/v) I off =10nA/µm DIBL, doping=3x10 20 cm -3 DIBL, doping=3x10 21 cm -3 I on, doping=3x10 20 cm -3 I on, doping=3x10 21 cm Ion (µa/µm) contact Source Source POLY POLY ~ ~ ~ ~ deep S/D junction depth (A) Shallow and highly doped Source/Drain is needed for high drive current and low DIBL

14 Outline Introduction Simulated device structure Source/Drain Engineering Contact depth effect in S/D region Conclusions

15 Source/Drain contact resistance Contact resistance can be major parasitic resistance component in nanoscale MOSFET device Contact resistance can be reduced by increasing silicide interface doping concentration and reducing schottky barrier height Φ B: ρ Exp( Φ c B * ε / N d ) Recessed contact depth effect on contact resistance 2 Long contact limit device: silicide-diffusion resistance is increased with contact depth increment in S/D region 2How about in short contact limit device?

16 Recessed Contact Depth Effect 720 spacer gate Drain Current (µa/µm) I on (µa/µm) Silicide 540 Junction Contact electrode depth in source/drain region (A) Unlike long contact limit case, Current drive capability is enhanced by increased contact depth in S/D region for short contact limit device Reason: current flows to both bottom and side of contact electrode

17 Optimized MOSFET Bulk Device POLY contact Source contact Drain Si substrate Device structure is optimized based on S/D series resistance, short channel effect and recessed contact depth effect Bulk device can be further scaled down below 45nm

18 Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions

19 Conclusions MOSFET Short Channel Effect is Source/Drain (S/D) electrostatic coupling result SCE is sensitive to SDE doping and junction depth, but it can be de-coupled from deep S/D region Doping concentration and length in SDE offset region is critical to S/D series resistance Shallow and highly doped S/D is expected for both I on and DIBL

20 Conclusions Unlike long channel device, SDE-to-Gate overlap in nanoscale device can be eliminated without degrading I on /I off performance due to velocity saturation limitation and S/D electric coupling effect Zero SDE-to-Gate overlap design can improve device speed in nanoscale MOSFET device Increased contact electrode depth in S/D region can enhance drive current in short contact limit case due to increased current spreading