Analog Performance of Scaled Bulk and SOI MOSFETs

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1 Analog Performance of Scaled and SOI MOSFETs Sushant S. Suryagandh, Mayank Garg, M. Gupta, Jason C.S. Woo Department. of Electrical Engineering University of California, Los Angeles CA 99, USA. Abstract This paper presents a systematic study of scaled MOSFET for analog/rf applications. An analog performance metric of intrinsic gain, f T, linearity, and g m /I ds ratio is considered. Impact of device scaling on this performance metric has been analyzed. Our study indicates that while scaling gate length (Lg) improves various trade-offs, scaling oxide thickness (T ox ) and source/drain extension junction depth (X j ) do not impact trade-offs significantly and they can be set by other constraints such as power supply and gate leakage currents. Also, it is shown that, even for the frequencies in the range of GHz (where AC kink effect is totally suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to capacitive drainto-body coupling and gate-workfunction engineering is essential in devices for improving analog performance at threshold voltage compatible with the bulk technology. As gate oxide is reduced to less than 2nm, gate leakage and the reduced supply voltage can seriously affect many analog circuits such as switch-capacitor or sample and hold circuits. The effect of gate oxide scaling and gate leakage currents on sample and hold circuits is therefore discussed in detail with reference to performance parameters such as non-linearity, acquisition time and droop rate. 1 Introduction Recent development in sub-1nm CMOS has resulted in transistors with cut off frequencies well above GHz [1, 2] which have started to replace silicon bipolar technologies in RF front end ICs, thus making tremendous progress towards SOC applications. However, for such mixed mode SOC applications, optimizing MOSFETs is challenging due to conflicting device performance requirements for digital and analog circuits. Speed-power trade-off which translates to optimizing I on /I off ratio and minimizing (CV)/I on are the primary goals for logic applications. For RF and analog circuits, intrinsic gain (g m xr out ), cut-off frequency (f T ), g m /I ds, linearity, noise and device mismatches constitute the performance metric [3]. Optimizing the device for one of them often leads to degradation in the others. Gate Current (Amps/cm 2 ) Gate Voltage (volts) Fig 1: Gate tunneling current for various T ox International Technology Roadmap for semiconductors (ITRS []) has two different scaling guidelines for analog and digital circuits, with analog device design lagging behind the digital by 3- technology generations. However, for mixed mode circuits in an SOC application, it is important to study the analog performance of the device optimized for digital circuit. Also, there are no definite guidelines for scaling SOI. MOSFETs for analog/mixed mode applications and the analog behavior of SOI devices in the GHz range, where kink effect is diminished, is not very clear. In this work, the impact of digital scaling on the analog performance of sub-1nm bulk and SOI MOSFETs at high frequency is discussed in detail using an analog metric of intrinsic gain, f T and g m /I ds. Another concern is gate leakage which degrades the performance of circuits which use CMOS pass gates to sample and transfer charge from input to output. In the case of S/H circuit, the gate leakage current increases the droop rate during the hold cycle and degrades the linearity of the sampled voltage. Therefore it is essential to understand the effect of scaling on the various components of the gate leakage current in order to alleviate undesirable charge sharing effects which degrade circuit performance. 2. Simulation Setup Experimental 13Å Tuned:Tox13Å Experimental 1Å Tuned:Tox1Å Experimental 18Å Tuned:Tox18Å In order to study the impact of scaling on analog performance of the nmosfets, extensive device simulations were performed using SILVACO s tools []. Channel lengths were varied from L g =nm to L g =2nm in order to compare the behavior between long channel and short channel MOSFETs. Two oxide thicknesses of 1.nm and 2.nm were used. Silicon thickness (T Si ) is kept fixed for devices at 6nm. Three X//$2. 2 IEEE.

2 different film thicknesses; 1, 2 and 3nm; were used for devices. Thinner silicon was not considered due to the uncertainty of bias currents, I ds =6µA/µm and 1µA/µm (same I ds instead of same overdrive, V gt = V g -V th, is chosen for the simulations as analog circuits are biased at same or ratioed currents). To simulate the gate currents, a calibrated model proposed by Cai, at. el. [6] was used in the simulator. Fig. 1 shows that the model agrees with experimental results [7] over a wide range of gate oxide thicknesses. Similar results are obtained for pmosfets. 3. Scaled MOSFETs performance g m /I ds, (V -1 ) g m /I ds, (V -1 ) 6 7. Lg=2nm e18 2e18 3e Doping, N A (cm -3 ) Lg=6nm. 8. I ds =1µA/µm 7. X j =1nm T 1. Si =1nm 1e18 2e18 3e Doping, N A (cm ) 3.1. Effect of Channel Doping (N A ) f operation =1GHz I ds =1µA/µm X j =1nm Fig. 2: Comparison of g m /I ds variation with channel doping in and SOI technologies long channel short channel devices Channel doping in a MOSFET is increased to control Short Channel Effects (SCE) and increase gate control for bulk as well as SOI technologies. g m /I ds variation of bulk and SOI technologies with the channel doping for long and short channel lengths is compared in Fig. 2 and 2 respectively. g m for a particular I ds decreases with increasing bulk doping due to mobility degradation. Long channel SOI devices exhibit higher value of g m /I ds than their bulk counterpart for channel doping higher than 1e17cm -3. It is more clearly demonstrated in the inset of he Fig. 2. This can be explained by the fact that SOI devices require smaller V gt and lower vertical electric field to achieve same I ds due to smaller effective body factor. Lower V gt implies smaller vertical electric field and hence higher mobility, result in an increases in g m /I ds. g m /I ds improvement in SOI devices increases with increasing channel doping as vertical electric field supports more depletion charge in this case. As the channel doping is reduced below 1e17cm - 3, mobility increases very slowly because its dependence on coulombic scattering is reduced. Hence, g m /I ds is relatively insensitive to doping. For dopings below 1e17cm -3, effect of parasitic source/drain resistance becomes important. High series resistance present in MOSFET due to thinner deep S/D regions degrades its g m /I ds compared to bulk MOS- FET (Fig. 2). For short channel lengths, as the channel doping is reduced below 1e17cm -3, g m /I ds decreases rapidly due to increased SCEs in bulk MOSFETs compared to as shown in Fig. 2. Fig. 3 and 3 show the comparison of output resistance for bulk and SOI technologies at operating frequency of 1GHz. In bulk MOSFETs, increased bulk doping reduces SCEs and increases R out. SOI devices have lower R out than bulk devices due to drain-to-body coupling. At high frequency, this coupling is determined by the ratio of drain-body capacitance and total body-ground capacitance. Total body-ground capacitance in MOSFETs (dominated by series combination of C ox and C Si due to interaction between front and back coupling) is higher than that in MOSFET (C BS, forward biased p-n junction capacitance). Reduced coupling in devices shows higher R out. SCEs severely degrade R out at lower doping and small channel lengths in bulk MOSFETs due to increased source/drain charge sharing. R out remains almost constant as the SCEs are effectively suppressed by the thin SOI body. At very low doping, R out of short channel MOSFET is limited by DIBL caused by drain fringing electric fields from buried oxide. This DIBL, to the 1 st order is unscalable with channel doping and silicon thickness. R out (Ω-µm) R out (Ω-µm) 3e 2e 1e 8e 6e e 2e f operation =1GHz I ds =1µA/µm X j =1nm Doping, N A (cm ) f operation =1GHz I ds =1µA/µm X j =1nm Doping, N A (cm -3 ) Fig. 3: Comparison of R out variation with channel doping in and SOI technologies long channel short channel devices

3 Fig. : Comparison of gain-f T relationships for and SOI technologies 3.2. Effect of L g Fig. shows gain-f T relationships for bulk and SOI technologies. Various points for a particular channel length are obtained by varying channel dopings. Decreasing channel doping increases g m and f T in bulk MOSFET; but severely degrades R out because of increased SCEs. Thus, there exists a trade-off between gain f T of a bulk MOSFET. On the other hand, increasing channel doping, does not improve R out of due to capacitive drain-body coupling. In the case of, increasing channel doping increases R out only slightly due to weaker dependence of SCEs on channel doping. Thus, SOI devices show higher gain as well as higher f T for low channel doping, a trend opposite to that shown by bulk MOS- FETs. For identical channel doping, V th of MOSFET is smaller than bulk and PDOSI MOSFET due to depletion charge confined by silicon thickness. In order to achieve V th ~.2-.3 V, suggested by ITRS, channel doping needs to be higher in. This causes degradation in intrinsic gain of MOSFET as shown by filled region in Fig.. Thus, in order to exploit the advantages presented by, novel gate workfunction engineering becomes necessary to allow both low channel doping and a V th ~.2-.3V Effect of T ox V th = V V th =-.2 - V for MOSFET L g =6nm g =1nm L g =1nm L g =2nm I ds =1µA/µm X j =1nm f oper =1GHz Gate control can be increased by increasing vertical gate electric field by using very thin gate dielectric. This increases g m due to increased channel inversion charge and R out due to better SCEs. However, high vertical electric fields causes mobility degradation. Thus, g m doesn t improve linearly with the increase in C ox. In order to maintain same V th when T ox is reduced, a higher N A is required. Therefore, both, improvement in intrinsic gain and degradation in f T become more pronounced. Fig. shows the effect of T ox on intrinsic gain vs. f T trade offs for various device lengths for the bulk MOSFET. Reducing T ox does not improve gain vs. f T trade-offs considerably and it can be set by the input swing (that is the maximum voltage across the oxide) consideration without degrading f T or gain. 1 g =6nm 8 g =1nm g =1nm L g =2nm 6 Ids=1µA/µm X j =1nm f oper =1GHz 2 Empty:T ox =2.nm Filled:T ox =1.nm V th ~.2-.3 V V L g =6nm th ~.2-.3 V g =1nm L 6 V th ~-.2- V g =1nm (Gate-Engineering) L g =2nm f oper =1GHz 2 Empty:T ox =2.nm Filled:T ox =1.nm Fig. : Effect of T ox on gain-f T relationship of bulk MOS- FET MOSFET As shown in Fig., for Vth~.2-.3 V, g m doesn t show any improvement for thin T ox and f T degrades as increased doping in thin T ox MOSFET decreases mobility (thereby nullifying the advantage gained by oxide scaling) and increases C gate respectively. Gain is higher for thin T ox devices as R out shows significant improvement. Also, degradation in f T for thin T ox is smaller in technology as channel doping is increased only by a small amount I ds =3µA/µm I ds =6µA/µm I ds =1µA/µm ds =1µA/µm I ds =2µA/µm L g =2nm L g =6nm (c) L g =2nm L g =2nm I ds =3µA/µm I ds =6µA/µm I ds =1µA/µm I ds =1µA/µm I ds =2µA/µm L g =6nm I ds =3µA/µm I ds =6µA/µm I ds =1µA/µm I ds =1µA/µm I ds =2µA/µm L g =6nm Fig. 6: Dependence of gain-f T curves on bias currents for MOSFET and (c)

4 Effect of I ds Output resistance of long channel bulk and MOSFET is mainly determined by CLM and drain-body coupling respectively. devices show strong dependence on both of these factors. As the drive current in increased, channel length modulation of a device increases. Long channel bulk and devices do not show any improvement in the gainf T trade-offs with increasing I ds as shown in Fig. 6,. The increment in f T caused by increasing I ds is cancelled out by the reduction in R out. Curves shift towards right i.e. improve for long channel MOSFET as shown in Fig. 6(c). For short channel, PD and FD MOSFETs, R out is mainly determined by DIBL, which has very weak dependence on V gt. Therefore, intrinsic gain of short channel devices experiences less severe degradation and gain-f T curve shift towards right. The improvement in f T is decreased at high currents due to velocity saturation and mobility degradation. Effect of X j I ds =1µA/µm L g =7nm V th =.1-.2V V th =.2-.V X j =1nm X j =1nm X j =2nm X j =3nm X j =3nm Fig. 7: Effect of X j on gain vs. f T trade offs for bulk MOSFET. Fig. 7 shows the gain vs. f T trade offs for bulk MOSFET as a function of X j for L g =7nm. f T and gain are varied by changing the substrate doping of the device. When X j is reduced, improvement in gain-f T trade-offs is initially seen. Such improvement gradually saturates and then the trade-offs degrade slightly as X j is reduced from 1nm to 1nm. The improvement in gain vs. f T trade-offs reduces at higher f T s (corresponding to devices with lightly doped substrates). At such low dopings, SCEs are mainly caused by deep S/D regions and the improvement in R out is mainly due to higher R S/D which is countered by degradation in g m due to severe SCEs. Therefore, gain does not improve significantly and we can conclude that X j has minimal effect on the gain-f T tradeoffs and its value can be set depending on other constraints such as ease of fabrication and junction leakage. 3.6 Effect of T si V th = V V th =-.2 - V for MOSFET I ds =1µA/µm L g =6nm L g =1nm L g =1nm L g =2nm T Si =2nm T Si =3nm Fig. 9: Effect of T Si scaling on gain-f T relationship in MOSFET. In devices, silicon thickness determines the amount of charge sharing and coupling between front and back gates. For the same channel doping, increased silicon thickness increases the depletion charge and vertical electric field before strong inversion. Also, surface conduction dominates for thick film devices. Thus, lower carrier mobility in thicker films reduces g m /I ds for higher doping as shown in Fig. 8. Significant degradation in R out is observed for short channel lengths, where increased silicon thickness increases source/drain charge sharing. Intrinsic gain is therefore better in thin film MOSFET with no significant change in f T. However, stringent requirement of keeping V th ~.2-.3V demands an increase in doping in thin film device. Therefore, f T of thin film devices is smaller in this range of threshold voltage due to mobility degradation. (Fig. 9). g m /I ds (V -1 ) Ids=1µA/µm L g =6nm L g =1nm L g =1nm Empty: L g =2nm Filled: T Si =2nm Channel Doping, N A (cm -3 ) Fig. 8: g m /I ds variation with N A for two different T si. Clock PFET Vin Source Drain sin(ωt) AC Source.V DC NFET Clock Fig 1: S-H circuit Vout Load Capacitor

5 Deep S/D Depth V s 3λ Xj Source L ov Gate V g T ox L g N A N S/D NSDE D V d T acq Acquisition Time (ps) Gate Oxide Thickness (Å) Droop Rate (Volts/sec) % change in Tacq W/o gate leakage W/ Gate leakage Gate Oxide Thickness (Å) Fig 12: Acquisition time and Hold voltage droop rate as a function of the gate oxide thickness. Fig 11: Device structure Gate current effects on S/H circuits In order to analyze the effects of gate leakage on S/H circuit, simulation is performed with a 2-D device simulator Medici running in circuit mode. The simple S-H circuit used in the simulation is shown in the Fig. 1 with the transistor (nmos- FET) cross-section shown in Fig. 11. The polysilicon gate devices have a fixed gate length of nm and oxide thickness, T ox, in the range of.8nm to 1.8nm. Substrate doping is varied to yield a V TH of.2volts. Uniform doping profiles and abrupt junctions were assumed for all the devices. The widths of the NMOS and the PMOS were set at 1µ m and 2µ m respectively to compensate for the mobility difference between the electrons and the holes. The clock voltage applied at the gate of MOSFETs has a period of 3ns (3.33Mhz), a realistic fall time of ns and a peak value of 1V. The input voltage is a.v peak to peak 2MHz sinusoid in series with a.v DC signal. The storage capacitor has a value of.3pf, which is approximately 1times the total gate capacitance (Cox) of the NFET and PFET, for a T ox of 1Å. A number of performance parameters are used in the analysis: (1) acquisition time defined as the time it takes for the voltage on the storage capacitor to reach 99.99% of its final value. (2) Integral nonlinearity, INL, which is the maximum deviation of the S-H output characteristics from a straight line for a linear increase in the input. For the quantification of this metric, a varying DC potential was applied to the source of the pass gate and the output was allowed to settle. After this, the pass gate was switched off and the sampled voltage measured. (3) The pedestal voltage which is the error introduced at the S/H output during the transition from sample to hold. () Droop rate which is the rate of discharge of the leakage capacitor during the hold mode. All the devices had a Vt of.2v..1 Effect of Gate Oxide Thickness Fig. 12 shows the variation of the acquisition time, T acq, with T ox. As it can be seen increasing Cox by 2X only results in about % improvement in T acq since the improvement in the drain current is not linear with respect to gate oxide thickness reduction (due to doping and vertical field induced mobility degradation). Fig. 12 shows the droop rate for different oxide thickness, with the gate tunneling model on and off. Since the gate tunneling current increases exponentially with reducing T ox, the storage capacitor discharge rapidly through gate leakage for thin T ox device. Fig. 13 shows the affect of gate oxide thickness scaling on the Integral Nonlinearity (INL). As can be seen, reducing the gate oxide thickness increases the non-linearity in the sampled voltages. This can be attributed to the increase in the channel charge injected (inset of Fig. 13) on the sampling capacitor as the gate oxide thickness is reduced..2 Effect of Junction Depth Ultra-shallow junction is needed to control short channel effects. However, small X j can lead to an increase in parasitic resistance and therefore an increase in T acq which is not affected by the gate leakage as seen in Fig. 1. The rise in the T acq is almost quadratic as the junction depth is reduced. Fig. 1 shows the sampled voltage droop rate for various junction depths. The fall in the droop rate is due to the enhanced source drain resistance which reduces the magnitude of V GD and therefore reduces the gate leakage current. Reduction in the droop rate is traded-off with the increase in the T acq ; reducing the X j from 2nm to 8nm increases the T acq by 6.6% whereas the droop rate reduces by 98%..3 Effect of Source Drain Extension Length Integral Nonlinearity (volts).x1-3.x1-3.x1-3 x1-3 3.x1-3 2.x1-3 V due to Charge Injection (mv) Crest w/o I G Trough w/o I G Crest w/i G Trough w/ I G T ox (Å) 2.x T ox Gate Oxide Thickness (Å) Fig 13: Integral nonlinearity as a function of the gate oxide thi k 3 2 INL measured at t=7.ns INL measured at t=.ns

6 T acq Acquisition Time (ps) % Change in Tacq 7 6 T acq for different X J Junction Depth (nm) Fig. 1, show the variation of the T acq with the SDE overlap length, L ov. Reducing L ov increases the R S/D and thus T acq. However, smaller (and negative L ov ) can improve the droop rate significantly as shown in Fig. 1 since the dominant gate tunneling current path during the hold mode is via the gate-source overlap region. The inset in Figure 1 shows the variation of the injected charge with the SDE overlap length. In the case of maximum sampled voltage (trough) the charge injection reduces with a reduction in the SDE overlap length, as the total channel current and charge reduces. However, in the minimum sampled voltage (crest) case, the gate tunneling current is reducing the effect of the channel injected charge. This is due to the fact that the tunneling current of the NFET acts to restore the additional charge deposited on the capacitor by the pass gate (mainly pmosfet due to its larger width). This is particularly true for long L ov where the gate tunneling current is significant. Fig. 16 shows the variation of the INL with L ov. We observe that the INL increases with L ov. Since the overlap capacitance increases with L ov, the charge injected onto the sampling capacitor and hence the nonlinearity increases. Conclusion Droop Rate (Volts/sec) Junction Depth (nm) In this paper, a detailed analysis of the analog performance of sub-1nm bulk and SOI technology is presented. The effects T acq Acquisition Time (ps) Droop Rate w/ Gate Leakage Trough w/o Gate Leakage Fig 1: Acquisition time and droop rate as a function of the source drain junction depth, all the devices have a T ox of 1Å and a Vt =.2V T acq for different SDE Droop Rate w/o Gate Leakage Droop Rate w/ Gate Leakage Source Drain Extension overlap (nm) Source Drain Extension (nm) Fig 1: Acquisition time and droop rate as a function of the SDE overlap length % change in Tacq Droop Rate (volts/sec) 16 Integral Non Linearity (mvolts) V (mv) Source Drain Extension (nm) of scaling of various device parameters on the analog performance were extensively studied through the defined analog metric. As L g is scaled down to sub-1nm regime, high values of f T can be achieved but it s difficult to achieve high intrinsic gain. Novel device engineering is required to improve R out of scaled devices. It is shown for the first time that doping has opposite effect on the gain-f T relationships of bulk and SOI technologies. Based on out study, we propose that gate workfunction engineering active body bias are essential to enhance the performance of thin film MOSFET. Severe drain-body coupling in MOSFET can be improved by using body-tied structure. The effects of gate oxide scaling on S/H circuit was examined. As T ox reduces, while T acq improves, the droop rate and the nonlinearity degraded. The excessive gate tunneling current and the reduced mobility are responsible for this behavior. It was shown that since the X j scaling had only a minor effect on the trade-offs between T acq, droop rate and INL, it should be set by constraints dictated by the ease of fabrication. It was shown that the nonlinearity and the droop rate increased dramatically for FETs with large SDE overlap regions, with only a marginal improvement in T acq. It was concluded that for a sample and hold circuit, small X j and L ov, with T ox as thick as permitted is desirable. References Crest w/o Gate Leakage Trough w/o Gate Leakage Crest w/ Gate Leakage Trough w/ Gate Leakage Source Drain Extension (nm) INL measured at t=7.ns INL measured at t=.ns Fig 16: Integral nonlinearity as a function of the SDE length. [1] G. Weinberger, ISSCC Tech. Dig., pp. 2-2, Feb. 2. [2] R-H. Yan, et. al., IEEE EDL, vol. 13(), pp. 26-8, [3]B. Razavi, IEEE JSSC, 3(3), pp. 268, Mar [] International Technology Roadmap for Semiconductor, 21 [] SILVACO International, Santa Clara, CA 9, USA. [6] J. Cai and C. T. Sah, JAP vol. 89, no,, 21. [7] C. Choi, et. al, IEEE TED vol. 8, no. 12, 21.