Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and

Transcription

1 Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body effect Did a review of small signal models Started small signal models for the FET In this lecture, we will Continue to build the small signal models for MOS FETs look at how MOS Transistors are modeled in SPICE 1

2 Reading We are next going to look at the analog characteristics of simple digital devices, And following the midterm, we will cover PN diodes again in forward bias, and develop small signal models: Chapter 6 we will then take a week on bipolar junction transistor (BJT): Chapter 7 Then go on to design of transistor amplifiers: chapter 8 Cutoff < > TN TP Linear TN TP,, Transistor equations: I D = 0 < Saturation > TN TP We discussed a physical model for these parameters, but often they will be used to fit the observed curves for a given manufacturing process I D = µ C ox W L 1 2 [( ) ] TN, TN 1 W 2 I D = C 2 ox T TP, TP L T 2 ( ) ( 1 ) µ + λ Note: if SB 0, need to calculate T 2

3 Circuit models We are now going to produce circuit models, which will translate the mathematics into drawings of circuit elements so that we can design real circuits using our developed intuition. Circuit models: In order to translate mathmatical expressions into an equivalent circuit, we will use resistors, capacitors, and variable current sources, hooking them up with perfect wires. Perfect wires have no parasitic capacitance or inductance, and convert into equations by Kirchoff s laws: i(t) + v(t) C R + v1 1 i 2 = gv 3

4 Large signal models: Large signal models try to recreate the behavior of real devices over large voltage swings, may not be linear, and may not be terribly accurate in the details. For example, a PN junction might be modeled as a perfect diode, which always blocks current in the forward direction, and passes current with no voltage drop in the reverse direction DC Large signal model for a FET Sometimes a circuit model is very close to mathematics, for example We can directly convert our mathematical model for the FET into: + + SB I D I D min GT Where: 0 = W k L = min = + SD (,, ) GT T GT min and 2 2 sat T min = ( 1+ λ ) T 0 + γ GT 0 2φ + f GT > 0 SB 2φ f 4

5 Typical parameters Here are some parameters for an actual 0.25 micron process: NMOS (olts) 0.43 (Root volts) 0.4 (volts) 0.63 (A/ 2 ) (volts -1 ) γ AT k λ T PMOS Limitations of large signal models Large signal models must often be greatly simplified to handle intuitively Large signal models are often nonlinear, so it is difficult to analyze circuits with more than a few elements directly Elements such as variable stored charge are difficult to model, often use a fixed capacitance which has a compromise value 5

6 Simplified large signal model To think about, and design circuits, we will often use rough models which behave somewhat like the physical device under a particular circumstance. For example we might model a FET as a resistive switch: G + D + C R Where C and R are chosen purely to give us an approximation to the observed value under the operating conditions S Small signal models If we linearize the model as discussed in the last lecture, by picking an operating point and allowing only small signal variations around those operating points (for both voltages and currents) we can produce a small signal model, one which includes only linear elements. This will let use linear circuit theory, which is a way we can handle very large numbers of interacting components. 6

7 Small signal model for the MOS FET The current from the drain of our FET can be modeled for small signals: i () t = I + i ds For a given operating point voltage for gs and ds, we get: Which we will then label: i i i = v + v ds gs ds vgs vds 1 i = g v + v r ds m gs ds o Transconductance Conductance Substrate potential Let s look at the back gate effect in a small signal model Effect: changes threshold voltage, which changes the drain current substrate acts like a backgate ℵ g mb i = v D BS ℵ i = v (,, BS ) are all held constant D BS ℵ 7

8 Backgate Transconductance ( ) T = T0 + γ SB 2φp 2φp Result: g mb id id Tn γ gm = = = v v 2 2φ BS Q Tn Q BS Q BS p Transconductance Notice that we have terms in our equations which give the small signal current into one terminal in as a constant times the small signal voltage into another terminal. In order to translate that into a linear equivalent circuit, we will use a variable current source, but where the current is just proportional to a voltage: + i 2 = gv v1 1 Where g is called the transconductance 8

9 Combining terms: Small-Signal Model We now have three small signal contributions to the current into the drain terminal for our FET, from changes in gs, bs, and ds 1 i = g v + g v + v r ds m gs mb bs ds o Notice that the change in the small signal current into the drain from A small signal change in ds can be modeled as a resistor. Capacitances While adequate for some purposes, the model so far implies that the current into the gate is zero. This is a good approximation for low frequencies, for high frequencies we need to account for the current necessary to charge up the gate to supply the field across the oxide. There are also stray capacitances to the drain and source contacts. 9

10 MOSFET Capacitances in Saturation The gate-drain capacitance is only the fringe capacitance when in saturation, because it is pinched off from the charge in the channel. Gate-source capacitance: There is fringing charge between the edge of the gate and the source, but also to the channel Gate-Source Capacitance C gs Wedge-shaped charge in saturation effective area is (2/3)WL (see H&S for details) C = (2 /3) WLC + C gs Overlap capacitance along source edge of gate C = L ov D WC (This is an underestimate, fringing fields will make The overlap capacitance larger) ox ox ov 10

11 Gate-Drain Capacitance C gd There is no contribution due to change in inversion charge in channel, just overlap capacitance between drain and source Junction Capacitances The source, gate, and drain will also have capacitances between them and the well or substrate. Capacitances to the drain and source will be junction capacitances, and since SB and DB = SB + reverse biases are different, the capacitances will be different 11

12 Seeking perfection Remember that all of the capacitances, resistances and transimpedances will change as the operating point changes There is no such thing as a perfect small signal model, use the simplest one that is sufficient. Sometimes a small signal model is used well outside of where it is accurate, because it is the main way we can deal intuitively with these devices! Junction Capacitances Drain and source diffusions have (different) junction capacitances since SB and DB = SB + aren t the same Complete model 12

13 P-Channel MOSFET Measurement of I Dp versus SD, with SG as a parameter: Square-Law PMOS Characteristics 13

14 Small-Signal PMOS Model Parameter variation The work that we have done so far implies that transistors will come out as we calculated, or at least with reproducible characteristics, however: Transistors from different manufacturers can be significantly different Transistor, resistance, and capacitor values will vary from batch to batch ~20% Parameters will vary to a lessor extent from wafer to wafer Transistors made close to each other on a wafer will be pretty similar, if W is not too close to the smallest available, and if they are close together. 14

15 Must design with wide tolerances To accommodate these wide variations in parameters, a LSI designer must design circuits which will work under a wide range of those parameters. We will study methods such as feedback which will tend to cause a design to operate as it should, even though the process parameters vary. SPICE A spice model is generally a set of formulas such as presented in this lecture, with the characteristics of the specific process set by parameters to the model. Several different models are available, indicated by the LEEL: Level 1: The Shichman-Hodges model, which is based on the long channel expressions given here. Level 2 model is a semiconductor physics model which includes velocity saturation, drain induced barrier lowering, etc. Level 3 is a semiemperical model which uses measured device data, and works well down to 1 micron channel lengths Many other models have been developed, mostly empirical 15

16 MOSFET SPICE Model we will use the square-law Level 1 model See H&S Spice refs. on reserve for details. SPICE level 1 parameters Even SPICE level 1 has many parameters, for example: TOX oxide thickness T0 threshold voltage LAMBDA channel length modulation parameter GAMMA bulk threshold parameter CD gate source overlap capacitance KP transconductance parameter Etc. Most parameters have reasonble defaults if values are not set explicitly 16