CHAPTER 3 TWO DIMENSIONAL ANALYTICAL MODELING FOR THRESHOLD VOLTAGE
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1 49 CHAPTER 3 TWO DIMENSIONAL ANALYTICAL MODELING FOR THRESHOLD VOLTAGE 3.1 INTRODUCTION A qualitative notion of threshold voltage V th is the gate-source voltage at which an inversion channel forms, which can then conduct a high drain current. With the continued down-scaling of all geometries to achieve the projected high packing density in submicron MOS devices, threshold voltage reduces with decreasing channel length. One of the key parameters that characterize short channel effects is the degradation of the devices threshold voltage with decreasing channel length. Therefore, the optimization of the threshold voltage is very important for both process and device engineers, and plays a major role for achieving a highly improved CMOS technology performance. Several models for the threshold voltage of short-channel FD SOI MOSFETs have been reported in the literature. Veeraraghavan and Fossum (1988) formulated a charge sharing model predicting threshold voltage dependence. The charge sharing modeling scheme assumes a constant surface potential, regardless of any drain bias, and therefore does not account for the drain bias associated with drain induced barrier lowering (DIBL). Additionally, because of the coupling effect between the front gate and the back gate, the charge sharing model by in (Veeraraghavan and Fossum 1988)
2 50 requires the use of a priori empirical fitting parameters, and therefore is not well suited for circuit analysis or statistical modeling. Woo et al (1990) and Guo and Wu (1993) developed short channel threshold voltage models by solving the two-dimensional (2D) Poisson s equation. However, due to the complexity of the solution and complicated mathematics required, physical insights into the dependence of short channel effects on the device parameters are masked. The dependence is an important factor needed by both process and device engineers to optimize the device short-channel effects. Banna et al (1995) used a quasi 2D approach and reported a threshold voltage model but it requires the use of an empirical fitting parameter which needs additional accurate measurements because small relative errors in measurements could give a large error in the fitting parameter value. Chen et al (2003) developed a compact, physical, short-channel threshold voltage roll-off of DG undoped devices, but that model did not include DIBL effects. Chen et al in (2003) and Suzuki et al (1996) presented models for the DIBL effect, but the devices considered were doped and the effect of the mobile charge density was neglected. It has to be remarked that undoped DG MOSFETs show better performance than doped ones, because of their higher mobility. In undoped devices, the effect of the mobile charge density cannot be neglected in the near-threshold regime. It was shown by Francis et al (1994) that even in doped DG MOSFETs, in order to apply standard methods of threshold voltage extraction, volume inversion should be considered when deriving a suitable expression of the threshold voltage.
3 51 The model by Munteanu et al (2006) addresses the DIBL effect in a DG MOSFET, but requires large iterations to obtain the expression of the electrostatic potential, from which a threshold voltage can be derived; on the other hand, this model is only valid for very thin Si films, since it assumes a longitudinal field which does not change along the depth of the film. Besides, it is also based on using an expression of the quasi- Fermi potential below threshold which was derived only for bulk MOSFETs, but which is adapted to DG SOI MOSETs using fitting parameters, the geometry dependence of them are not clear. Liang and Taur (2004) presented a 2-D analytical solution for short- channel effects in undoped DG MOSFET; the mobile charge was neglected to solve the2-d Poisson s equation. This approximation is valid well below threshold (the regime in which the model of the threshold voltage roll-off, DIBL and sub threshold slope are calculated), but near threshold, the mobile charge has an effect on the electrostatic potential. Most of the existing SG MOSFET models are based on one dimensional (1-D) analysis, and are suitable only for long channel devices (Iniguez et al 2005). Consequently, they cannot produce the roll- off as the channel length is reduced. A two-dimensional analysis is necessary to derive threshold voltage and sub threshold swing models that properly account for the channel dependence. A few 2-D models of the threshold voltage for doped (Kranti 2001) and undoped SG MOSFETs have been developed. However all of them neglect the effect of the mobile charge density, which can be important in the near threshold regime (in particular for undoped devices). Auth and Plummer (1998) proposed a simple model for the threshold voltage of the surrounding gate MOSFETs. Due to their threshold voltage model based on the long-channel device with the simulation-based
4 52 short-channel effects, it is insufficient in offering the physical and analytical model for the small geometry devices. Kranti et al (2001a) proposed a threshold voltage model based on 2-D potential analysis. However, the expression of the threshold voltage is too complicated to be used in the physical device analysis that is essential for the device engineer in designing the SG MOSFETs and is overshadowed by their complicated and implicit formula. Kranti (2001b) et al suggested a two-dimensional analytical model for the thin film fully depleted SG MOSFET. The model only focuses on the potential analysis of the silicon film and took no consideration of the potential of the gate oxide, which helps to precisely analyze the threshold voltage especially for the short and thick MOSFETs. In this Chapter, an analytical expression of threshold voltage is derived for a fully depleted DMSG SOI MOSFET based on the twodimensional surface potential model that was developed and explained in Chapter 2. The mathematical formulation aids in quick visualization of the importance of various device parameters on the performance of a DMSG SOI device and allows for a good grip on the underlying device physics. The efficiency of the DMSG structure in subduing the short-channel effects (SCE) is also studied in relation to various device parameters. 3.2 PROPOSED THRESHOLD MODEL FOR DMSG DEVICES Threshold voltage V th is that value of the gate voltage V GS at which a conducting channel is induced at the surface of SOI MOSFET. In a fully depleted thin-film SOI, it is desirable that the front channel turns on before the back channel. Therefore, the threshold voltage is taken to be that value of
5 53 gate source voltage for which s z 2 F min where F is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level. In the case of DMSG structure, due to the co-existence of metal gates, M1 and M2, with different work functions, the surface potential minima are solely determined by the metal gate with higher work function. So the threshold voltage is defined as the value of V GS at which the minimum surface potential equals 2. Hence we can determine the value of threshold voltage as the value of V by solving: Q 1 z min 2 AB 2 S (3.1) P Using equation (2.16), and solving for V th L L 2 4KM V th (3.2) 2K where, the constant coefficients are given below K exp( 2PL) 1 (3.3) qn qn a a L 2V V V bi DS FB 2Vbi V 2 2 FB exp F sinh si P si P M Vbi V DS PL 4 PL qn qn qn a a V FB Vbi V 2 2 FB exp F F 2 FB sinh sip sip sip (3.4) a 2 2PL 4 V PL (3.5) The dependence of V th on the length and material workfunction of the two gate metals is a significant result of the above formulation. This feature which is unique to DMSG SOI lends another degree of freedom
6 54 towards controlling and engineering the threshold voltage of ultra small SOI transistor design. The formulation of surface potential, however, assumed the absence of mobile charge carriers in the channel to simplify the subsequent analysis. Therefore, the threshold voltage expression derived is not strictly based on the common notion of V th which indicates a physical background of moderate inversion, i.e., the transition between weak and strong inversion. A more rigorous analysis involves solving the 2-D Poisson s equation taking the mobile carrier density into account (in addition to the depletion charge) but that would lead to a computationally inefficient analytical model requiring the use of fitting parameters. 3.3 RESULTS AND DISCUSSIONS To verify the proposed analytical expression, the calculated values of threshold voltage from the model are compared with those obtained from 2-D MEDICI (1997) simulation Threshold Voltage Dependence on Drain Source Voltage Figure 3.1 shows calculated and simulated values of threshold voltage with channel length for different drain-source voltages of the DMSG structure. It is observed that the threshold voltage along the channel length can be considerably decreased by increasing drain-source voltages. The threshold voltage shows a roll-up with reducing channel lengths. The linear threshold voltage, is based on the maximum transconductance method at V DS = 0.5V. The saturation threshold voltage is based on a modified constantcurrent method at V DS = 1 V where the critical current is defined as the drain
7 55 current when V GS = V th,lin. The step profile ensures that the drain potential is screened and the surface potential minima at the source end remains effectively unchanged which accounts for the reduction in DIBL. The model predictions correlate well with the simulation results proving the accuracy of our proposed analytical model. Figure 3.1 Threshold voltage versus channel length of the DMSG MOSFET for different drain-source voltages Threshold Voltage Dependence on Built in Voltage Figure 3.2 shows that calculated and simulated values of threshold voltage with channel length for different built-in voltages of the DMSG structure. When built in voltage is varied, the threshold voltage increases. As shown in the figure for both oxide thicknesses, V th rolls-up at shorter channel lengths. Thus the DMSG structure lends another degree of flexibility in the
8 56 design of deep submicron SOI transistor design by offering the alternative of gate material engineering to subdue the undesirable SCE. Figure 3.2 Threshold voltage variations with channel length for DMSG MOSFET by varying built-in biases Comparison With DMG Structure Figure 3.3 shows that calculated and simulated values of threshold voltage with for DMSG structure. The calculated threshold voltage model for the DMSG is also included for comparison. This unique feature of the DMSG structure is an added advantage when the device dimensions are continuously shrinking. With decreasing channel lengths, it is very difficult to fabricate precise channel lengths. A threshold voltage variation from device to device is least desirable. The DMSG structure exhibits a threshold voltage that is almost constant with decreasing channel lengths. From the results it is clearly
9 57 seen that the calculated values of the analytical model tracks the simulated values very well. Figure 3.3 Threshold voltage variations as a function of channel length for DMG and DMSG MOSFETs L1/L2 Ratio Dependence Figure 3.4 shows the variation of threshold voltage with workfunction difference at a fixed channel length of L = 0.5 µm for two L 1 /L 2 ratios as predicted by the analytical expression and the 2-D numerical simulations. As shown in the figure, threshold voltage increases with increasing workfunction difference. The dual-material surrounding gate (DMSG) structure offers the benefit of SCE suppression in a SOI device by virtue of gate material engineering, i.e., engineering the length and workfunction of the two gate metals. For a fixed workfunction difference,
10 58 threshold voltage is higher for a higher L 1 /L 2 ratio due to the increased proportion of the channel region controlled by a higher work function gate. Figure 3.4 The dependence of Threshold voltage on channel length for different L 1 / L 2 Combinations Radius Variation Figure 3.5 shows the variation in radius with fixed channel length. The variation of the front-channel minimum potential as a function of channel length (L=L 1 +L 2 ) for fully depleted DMSG SOI with silicon thin-film thickness R = 40 nm and 20 nm is shown. In fully depleted (FD) MOSFET, the minimum channel potential is sensitive to thin-film thickness. But as observed from the figure, the dependence of minimum channel potential on radius R, and consequently threshold voltage, is effectively reduced due to the co-existence of gate materials having a finite work function difference in a
11 59 DMSG SOI MOSFET. The results have been compared with the simulated results obtained from the MEDICI simulation software (1997), and a good agreement is achieved between the two. Figure 3.5 The dependence of Threshold voltage on channel length for different Silicon thicknesses Comparison with Chiang Model Figure 3.6 shows the comparison of proposed model and MEDICI with Chiang model by taking R= 30nm. From the plots, the DMSG MOSFET exhibits a peak electric field away from the drain side which therefore causes a uniform field along the channel and reduces the hot carrier effects (HCEs). The proposed model will give the peak field almost near the drain side and bring about severe HCEs that causes tremendous drain leakage current.
12 60 The result is shown that the proposed model provides an improved performance over the Chiang model (2007). Figure 3.6 Graph for the threshold voltage versus channel length. The calculated threshold voltage model by Chiang (2007) for the DMSG is also included for comparison Scaling Characteristics In Figure 3.7 the calculated values of threshold voltage as a function of channel-length are compared with those obtained from MEDICI simulations. It is seen that the threshold voltage obtained from the analytical model tracks the simulation values very well but with an insignificant negative offset of approximately mv. This less than 10% discrepancy in the results is due to the neglect of the inversion layer charge at threshold at
13 61 the front interface. This is due to the presence of two different gate metals having a finite workfunction difference and carefully chosen gate lengths. Figure 3.7 Threshold voltage variations with channel length compared for DMSG, DMG and SMSG SOI devices Thin-film doping dependence Figure 3.8 shows the threshold voltage variation with decreasing channel length obtained from the value calculated using the analytical expression and MEDICI simulation for two different body doping densities. As shown in the figure, threshold voltage increases with increased body doping and a roll-up in the characteristics is observed at decreasing channel lengths. This can be attributed to the presence of two different gate materials having a finite workfunction difference and properly engineered gate lengths.
14 62 As shown in the figure the results from the analytical model are in close proximity of the simulation results. Figure 3.8 Threshold voltage variation with channel length for different body doping density 3.4 CONCLUSION An analytical expression of threshold voltage for a fully depleted DMSG SOI MOSFET is formulated based on the 2-D physical model of surface potential developed earlier. The effect of various device parameters like gate length scaling, body doping density, the lengths of the gate metals and their work functions, substrate biasing, the thickness of the buried oxide on the threshold voltage are studied. The results predicted by the model are compared with 2-D simulations. The results clearly demonstrate the excellent immunity against SCE offered by the DMSG structure with a V th roll-up with
15 63 decreasing channel lengths visible down to 0.1 µm. Moreover the immunity against SCE is possible by a new way of gate material engineering which lends a tremendous flexibility in deep submicron SOI design. The results provide incentive to further investigate the potential benefits of a DMSG SOI over a conventional SOI MOSFET for its possible integration in the CMOS technology.
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