Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP)

Transcription

1 Science in China Series E: Technological Sciences 2009 SCIENCE IN CHINA PRESS tech.scichina.com Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP) LUAN SuZhen, LIU HongXia & JIA RenXu Key Laboratory of Ministry of Education of China for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi an , China Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node. The higher f T of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally, the design guideline and the optimal regions of the DMGDP MOSFET are discussed. dual material gate (DMG), dielectric pockets (DP), short-channel effect (SCE), cutoff frequency 1 Introduction With complementary metal-oxide-semiconductor (CMOS) scaling to the end of the roadmap ( leakage current and short-channel effects (SCE) have become the major scaling challenges. In current deep submicron CMOS technology and beyond, pocket implantation [1 4] appears to be a commonly used strategy for suppressing SCE. However, it presents many inconveniences such as an increase of the body factor and junction capacitance as well as the junction leakage current [5]. In order to solve all of the above-mentioned problems, the concept of dielectric pockets has been proposed [6]. Nevertheless, for ultimate scaled CMOS devices, the efficiency of transport is another problem to be solved. Dual-material gate (DMG) MOSFETs [7,8] seem to be a very promising option for enhancing the transport efficiency. In this paper, the comprehensive study on the characteristics of the DMGDP MOSFET has been performed. A scheme for fabrication of the novel structure is pre- sented. The capability of the SCE suppression is investigated and compared with the DP MOSFET. The direct current (dc) and alternating current (ac) characteristics of the DMGDP MOSFET are analyzed in detail. The results show that the performance can be significantly improved due to the high drive current and the decrease of the parasitic resistance and capacitance. Finally, the scaling capability and design guideline of the DMGDP MOSFET are discussed in detail. 2 Device structure and fabrication The schematic cross-sectional view of the DMGDP NMOSFET is shown in Figure 1(a). For comparison, the conventional DP MOSFET is demonstrated in Figure 1(b). As shown in Figure 2, the basic process to realize Received December 5, 2007; accepted January 12, 2008; published online October 11, 2008 doi: /s Corresponding author ( szluan@mail.xidian.edu.cn) Supported by the National Natural Science Foundation of China (Grant No ), Program for the New Century Excellent Talents of Ministry of Education of China (Grant No ), and the National Defense Pre-Research Foundation of China (Grant No ) Sci China Ser E-Tech Sci Aug vol. 52 no

2 Figure 1 Schematic cross-sectional view of the devices. (a) The DMGDP NMOSFET; (b) the DP NMOSFET. Figure 2 Key fabrication steps of the DMGDP MOSFET. such a device structure can be given as follows. After classical shallow trench isolation (STI) process shown in Figure 2(a), nitride deposition is followed by oxide film, as shown in Figure 2(b). The nitride layer acts as a sacrificial layer which defines the silicon film thickness and oxide layer serves as a sacrificial gate. Anisotropic plasma etching of SiO 2 /Si 3 N 4 -Si is performed to define the future source/drain (S/D), as shown in Figure 2(c). The depression determines the depth of dielectric pockets. The exposure of silicon grows oxide which forms the isolation near the S/D region, as shown in Figure 2(d). Then, nitride is removed by wet etching, as shown in Figure 2(e). It requires fine tuning of the overetching step during the wet etching process. The height of the dielectric pockets determines not only the thickness of the contact region between extensions and highly doped (HD) S/D regions, also the S/D junction resistances. On the other hand, if the dielectric pocket is too high, there is no longer connection between S/D and the channel, thus the on-state current (I on ) drops rapidly to zero. The selective epitaxial silicon is grown out of the seed window through the tunnel and fills all the recessed areas. Chemical-mechanical polish (CMP) is carried out to remove the excess epi-silicon using the top oxide as a polish stop layer as shown in Figure 2(f). The top oxide is removed by wet etching and followed by the formation of spacers, as shown in Figure 2(g). The gate oxide is grown and the patterning of the gate is followed by the implantation of S/D in Figure 2(h). Finally, the annealing of rapid thermal processing (RTP) will be performed. It is emphasized that the definition of the dual material gate requires additional processing steps in order to laterally form two well-controlled contacting gate materials. Here, the technology mentioned in ref. [8] was adopted for the gate formation, which is shown in Figure 2(i). Besides, in order to ensure the connection between S/D regions and the channel, Si epi-layer should be thicker than the depth of the formed depressions. This resulted in the elevation of S/D regions. It is also mentioned that, contrary to many reported devices with elevated S/D (e.g. ref. [9]), which suffer from faceting at the edge of the epitaxial silicon, in our device this problem does not occur. The lack of facets is probably due to the fact that the extremity of the channel LUAN SuZhen et al. Sci China Ser E-Tech Sci Aug vol. 52 no

3 (above the buried spacer) constitutes an additional seed for starting the epitaxy process directly at the bottom of the upper spacer in addition to the seed at the bottom of the trench. 3 Results and discussion The device structures are created and simulated by the two-dimensional device simulator Silvaco. The dope of the S/D is a dose of cm 2 with arsenic (for NMOS) and boron (for PMOS). The S/D terminals are treated as ohmic contacts in the simulation. Since the effects of work function of metals on the device characteristics have been reported widely, the effect of the work functions for both metals here on the devices will not be considered. The characteristics of devices have been simulated through self-consistent solution of Poisson, continuity, and hydrodynamic model, which provides an accurate simulation for transistors with ultra-short channels. Figure 3 shows that the DMGDP MOSFET has the improved suppression of the SCE compared with the DP MOSFET. It is worth noting that the effect of the drain induced barrier lowering (DIBL) is greatly alleviated by the DMGDP MOSFET and the shifts of the threshold voltage are much less than those of the DP devices. This advantage results from the fact that the metal gate near the drain end screens the effect of drain bias on the source region. Figure 4 shows the surface potential profile along the channel for the DMG architecture and DP NMOSFET. It is apparently noticed that the DMG MOSFETs have step potential along the channel, which results from the different work function metal gates. Assume that the lengths of the two gate materials are L c (control gate, with higher work function or threshold voltage) and L s (screen gate, with lower work function or threshold voltage), respectively. Due to the existence of the screen gate, the effect of drain bias on the source region is screened. In other words, it is as if the drain bias is absorbed by the screen gate. It can be seen from the figure that for the DMGDP MOSFET, an extra potential step profile exists near the dielectric pocket boundary in addition to the one near the interface between the two gates in the DMG. It is further identified that the DMGDP MOSFET has the improved suppression of the DIBL effects. In addition, the charge sharing of the S/D with the channel and the leakage current of the S/D junction decreases due to the isolation layers near the Figure 3 SCE in the DMGDP and DP NMOSFETs. (a) DIBL; (b) threshold voltage roll-off. Figure 4 Distributions of the surface potential for the 100 nm DMG and DP MOSFETs. S/D regions. The transfer characteristics of the 0.16 µm DP PMOS transistor between experimental data and simulation results are compared in Figure 5. It can be seen that the simulation results provide a good agreement with the experimental data. Thanks to dielectric pockets, the lateral diffusion of highly doped S/D is blocked and the off-current can be significantly reduced. However, due 2402 LUAN SuZhen et al. Sci China Ser E-Tech Sci Aug vol. 52 no

4 Figure 5 Comparison between experimental data and simulation results for the I ds V gs curves of 0.16 µm DP PMOSFET. to the dielectric pockets, the current flows in the channel seem limited. Thus, the drive current cannot be improved without modifying the structure of these transistors. The introduction of DMG into the DP MOSFET can indeed increase the on-state current. As shown in Figure 6, the saturation current normalized to the V gs = V th 1.8 V is 305 µa/µm for dielectric pockets alone and 601 µa/µm for the device with DMG. The on-state current for the DMGDP MOSFET is almost the twice that of the DP MOSFET. The improvement of on-state current is due to the existence of the extra electric field peak near the interface of both metals. Thus, the overshoot velocity occurs near that region. Slightly lower on-current of 535 µa/µm, obtained in devices without the lightly doped drain (LDD) is attributed to the difference in the effective gate length. The improvement of on-state current is due to the existence of the extra electric field peak near the interface of both metals (see Figure 7). The conventional DP MOSFET has a single peak of electric field. In the conventional MOSFET, electrons enter the channel with a low initial velocity, gradually accelerating toward the drain, and the maximum electron drift velocity is Figure 6 Drain current against gate voltage for 0.16 µm PMOSFET. Figure 7 Electric field variation with the distance along the channel for the DP and DMGDP MOSFETs. reached near the drain. Hence, the speed of the device is affected by a relatively slow electron drift velocity in the channel near the source region. The DMG MOSFET seems to be a very promising option for enhancing the transport efficiency. Work function difference of the two metal gates causes an abrupt change in the conduction band energy at the silicon surface, which provides an electric field peak in the channel, and gives greater acceleration to the carriers. In Figure 7, the first peak occurs (50 nm near the source) just where the step potential occurs in the DMGDP MOSFET. The peak value is as much as 0.5 MV/cm, which is increased by about one order of magnitude compared to the DP MOSFET. Such high electric field accelerates the injected electrons. Therefore, the carrier injection effect is enhanced. Moreover, the second peak near the drain in the DMGDP MOSFET decreases greatly compared to the DP MOSFET due to the absence of potential gradient under the screen gate. The dielectric pocket near the drain maybe contributes to this phenomenon. As a result, the lower electric field decreases the risk of the avalanche impact at the drain/substrate junction, thus reducing hot carrier effects (HCE). The electric field of the DMGDP device near the source region is higher than that of the DP device, opposite near the drain, thus improving the electron velocity and HCE simultaneously. In order to further prove the above arguments, the electron velocity distributions for the DMGDP and the conventional DP MOSFETs are also shown in Figure 8. It has been seen that in the DMG device the velocity maximum near the source is about cm/s. Such high velocity plays a predominant role in the overall carrier transport efficiency of the MOSFET. The DMG structure has the advantages of increasing driving current (Ion) and transconductance (gm) over the DP MOSFET. LUAN SuZhen et al. Sci China Ser E-Tech Sci Aug vol. 52 no

5 Figure 8 Electron velocity variation of the DMGDP and DP structures with the distance along the channel. Considering the factors mentioned above, the DMGDP MOSFET shows a great potential in high- performance applications. Figure 9 illustrates the intrinsic delay metric C gate V DD /I on with the 32 nm channel length compared with DP for NMOSFET and PMOSFET, respectively. It can be clearly seen that the DMGDP exhibits significant performance enhancement. The performance enhancement of NMOS reaches 21% greater than that of the DP MOSFET. It is worth noting that the intrinsic delay of DMGDP MOSFET is smaller than the specification of the high performance application of ITRS 06 and this represents a further significant advantage. Due to the lower mobility of the hole, the intrinsic delay of the PMOS increases. There is still about an 18% performance enhancement for the PMOS of the DMGDP MOSFET compared with the DP PMOSFET. the small-signal simulation. Figure 10 shows the comparison of the cutoff frequency f T with DP and DMGDP MOSFETs as a function of gate length. It can be clearly seen that the cutoff frequency reaches to several hundreds GHz with the gate length below 100 nm. The cutoff frequency of 295 GHz is obtained by the DP NMOSFET device with the 50 nm gate length. The higher f T of 390 GHz is achieved which is a 32% enhancement in comparison with the DP MOSFET. The DMGDP device has higher cutoff frequency, and this advantage becomes more remarkable as the gate length decreases. In spite of the low mobility of the hole, the cutoff frequency of the DMGDP PMOSFETs is also more than 100 GHz. The improvement of f T is attributed to the decrease of the parasitic capacitance (these capacitances may be due to the overlaps for gate/source and gate/drain, or the junction capacitance for the S/D with substrate). It indicates that the DMGDP structure is more suitable for the wide range application. Figure 10 Comparison of the cutoff frequency f T with the DP and DMGDP MOSFETs as a function of gate length. Figure 9 Comparison of the intrinsic delay between the DP and DMGDP MOSFETs with the physical gate length of 32 nm. In order to analyze the RF characteristics, the cutoff frequency f T is extracted from the forward current gain (H 21 ) of both the DP and DMGDP device structures by In order to analyze the scaling capability and the impact of the DMGDP structure on the specifications of ITRS, Figure 11 presents the variations of the I on I off with the technology nodes from the 100 nm node to the 32 nm node. An extensive investigation is performed to achieve the performance of the DMGDP MOSFET, with the other results coming from the ITRS 06. Comparing the DP devices sufficient for satisfying the 100 nm and 90 nm nodes for the high performance specifications, respectively, the DMGDP structure shows a clear advantage down to 50 nm node. With the same subthreshold leakage current, the DMGDP structure has a higher drive current than the specifications of ITRS 06. There 2404 LUAN SuZhen et al. Sci China Ser E-Tech Sci Aug vol. 52 no

6 Figure 11 Impact of the DMGDP structure on ITRS 06 specifications with all the parameters according to the ITRS 05. after, the device performance deteriorates because of the reduced V dd. From the schematic cross-sectional view of the DMGDP structure shown in Figure 1, h 1 and h 2 are the main parameters which have great influence on the characteristics of the device. The distance between the isolation and the surface of the channel (h 1 ) has influence on the drive and the leakage current which needs the optimization on the decision of the h 1. The thickness of the isolation (h 2 ) mainly decides the decrease of the parasitic capacitance and the increase of the parasitic resistance. Both h 1 and h 2 have the great influences on the suppression of the SCE. Figure 12 shows the influence of the two main parameters on the I on and I off of the DMGDP device of the 50 nm gate length. From the specifications of the I on and I off of the ITRS 06, Figure 13 presents the optimization regions for the 50 nm gate channel. It is worth noting that the DMGDP structure can satisfy the requirements of the ITRS through the modulation of the work function of the metal gate. Figure 12 Influence of the two main parameters (h 1 and h 2 ) on the I on and I off of the DMGDP device with the 50 nm gate length. Figure 13 Optimization regions for the DMGDP MOSFET with 50 nm gate length. 4 Conclusion The characteristics of the DMGDP MOSFET were investigated by an extensive simulation study compared with the DP MOSFET. Not only can the DMGDP structure suppress the SCEs, but also it can eliminate the electric potential coupling via the depletion region of the DP MOSFET. The DMGDP MOSFET shows a great potential in the high performance applications and achieves the greater cutoff frequency f T of 32%. Considering the impact on the ITRS specification, the DMGDP structure shows a clear advantage down to the 65 nm node. Finally, the optimization regions for the 50 nm gate length are given. There is a wide design window to achieve the ITRS specifications with the 50 nm gate length and beyond. 1 Goto K, Kase M, Momiyama Y, et al. A study of ultra shallow junction and tilted channel implantation for high performance 0.1 mm pmosfets. In: IEDM 98 Tech Dig, San Francisco, America, 1998, Gwoziechi R, Skotnicki T, Bouillon T, et al. Optimization of V th roll-off in MOSFETs with advanced channel architecture-retrograde doping and pockets. IEEE Trans Electron Devices, 1999, 46(7): Gwoziechi R, Skotnicki T. Smart pockets-total suppression of roll-off and roll-up. In: 10th Symposium on VLSI Technology, Kyoto, Japan, 1999, Togo M, Tanabe A, Furukawa A, et al. A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs. In: 7th Symposium on VLSI Technology, Honolulu, HI, USA, 1996, Hwang H, Lee D H, Hwang J M. Degradation of MOSFETs drive current due to halo ion implantation. IEDM Tech Dig, 1996, Jurczak M, Skotnicki T, Gwoziecki R, et al. Dielectric pockets a new concept of the junctions for deca-nanometric CMOS devices. IEEE Trans Electron Devices, 2001, 48(8): Saxena M, Haldar S, Gupta M, et al. Design considerations for novel device architecture: hereo-material double-gate (HEM-DG) MOSFET with sub-100nm gate length. Solid State Electron, 2004, 48(7): Long W, Ou H, Kuo J M, et al. Dual material gate (DMG) field effect transistor. IEEE Trans Electron Devices, 1999, 46(5): Yamakawa S, Sugihara K, Furukawa T, et al. Drivability improvement on deep-submicron MOSFETs by elevation of source/drain regions. IEEE Electron Device Lett, 1999, 20(7): LUAN SuZhen et al. Sci China Ser E-Tech Sci Aug vol. 52 no