Record I on (0.50 ma/μm at V DD = 0.5 V and I off = 100 na/μm) 25 nm-gate-length ZrO 2 /InAs/InAlAs MOSFETs

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1 Record I on (0.50 ma/μm at V DD = 0.5 V and I off = 100 na/μm) 25 nm-gate-length ZrO 2 /InAs/InAlAs MOSFETs Sanghoon Lee 1*, V. Chobpattana 2,C.-Y. Huang 1, B. J. Thibeault 1, W. Mitchell 1, S. Stemmer 2, A. C. Gossard 2, and M. J. W. Rodwell 1 1 ECE and 2 Materials Departments University of California, Santa Barbara, CA 2014 Symposium on VLSI Technology Honolulu, Hawaii, USA 06/10/2014 *sanghoon_lee@ece.ucsb.edu 1

2 Why III-V MOSFETs in VLSI applications? Low m* in III-V material high v inj high transconductance More transconductance per gate width more current lower intrinsic delay -or- reduced V DD less power consumption -or- small FETs reduced IC size TW. Kim, IEDM 2012 Other advantages Wide range of available materials nm-precise growth 1-2 nm thick channel Larger ΔE c Better confinement, Small EOT 2

3 Key Design Considerations Source/Drain: Low ρ c Small contact size Self-aligned Small contact pitch Shallow Scaling (electrostatics) Dielectric: Thin high I on, better SS and DIBL Low D it Better SS N+Source Dielectric Channel N+Drain Barrier Channel: Thin Electrostatics Thin and wide bandgap Small band-band tunneling Thick and narrow bandgap higher injection velocity 3

4 FET Structures N+Source Dielectric Body N+Drain Inversion layer N+Source Dielectric Barrier Channel Barrier N+Drain N+Source Dielectric Channel Barrier N+Drain Etch stop Inversion mode MOSFETs - Self-aligned - Implant damage - Large R access (limited doping) MOS-HEMT - Good short channel effect - Large device footprint - Large R access (Barrier) Trench-etch - Small footprint - Small R access - Limited L g scaling (wet etch) N+Source (Regrown) Regrown S/D with gate-first Dielectric Channel Barrier N+Drain (Regrown) Regrown S/D with gate-last - Small footprint and L g - Small R access - Abrupt junction - High damage (gate-stack etch) - Low damage (No dry etch) 4

5 Gate-Last Process ( Simplified for Development ) Channel growth By MBE Dummy gate formation e-beam lithography Vertical spacer and N+ S/D regrowth in MOCVD Cap: 2 nm In 0.53 Ga 0.48 As (U.I.D) Channel : 3.5 nm InAs (Strained) Setback: In 0.52 Al 0.48 As Setback (U.I.D) Pulse Doping (Si 2X10 12 /cm 2 ) Back Barrier: In 0.52 Al 0.48 As (U.I.D) P-type Doped Barrier: In 0.52 Al 0.48 As (Be /cm 3 ) HSQ Al 2 O 3 InGaAs Cap InAs Channel In 0.52 Al 0.48 As Setback In 0.52 Al 0.48 As Back Barrier P-type Doped Barrier Pulse Doping 50 nm N+ In 0.53 Ga 0.47 As HSQ In 0.52 Al 0.48 As Back Barrier P-type Doped Barrier Regrown S/D 10 nm In 0.53 Ga 0.47 As Al 2 O 3 Vertical Spacer InGaAs Cap InAs Channel In 0.52 Al 0.48 As Setback Pulse Doping Substrate: InP (Semi-insulating) InP (Substrate) InP (Substrate) Mesa-isolation Surface digital etching N+ In 0.53 Ga 0.47 As Regrown S/D 12 nm In 0.53 Ga 0.47 As 2.5 nm InAs Channel In 0.52 Al 0.48 As Setback In 0.52 Al 0.48 As Back Barrier P-type Doped Barrier Vertical Spacer Pulse Doping Gate stack formation 0.7/3.0 nm Al 2 O x N y /ZrO 2 N+ In 0.53 Ga 0.47 As Ni/Au (gate metal) Regrown S/D 12 nm In 0.53 Ga 0.47 As Vertical Spacer 2.5 nm InAs Channel In 0.52 Al 0.48 As Setback In 0.52 Al 0.48 As Back Barrier Pulse Doping P-type Doped Barrier S/D metal contact formation Ti/Pd/ Au 0.7/3.0 nm Al 2 O x N y /ZrO 2 (S/D metal) Ni/Au N+ In 0.53 Ga 0.47 As (gate metal) Regrown S/D 12 nm In 0.53 Ga 0.47 As L SD L g 2.5 nm InAs Channel In 0.52 Al 0.48 As Setback In 0.52 Al 0.48 As Back Barrier P-type Doped Barrier Vertical Spacer Pulse Doping InP (Substrate) InP (Substrate) InP (Substrate) 5

6 High-k : MOSCAP with 0.7/5.0 nm Al 2 O x N y /ZrO 2 Ni/Au 54 nm ZrO 2 ~0.7 nm Al 2 O x N y N-type In 0.53 Ga 0.47 As N-type InP (Substrate) Cr/Au MOSCAP structure dielectric constant for ZrO 2 is 23; EOT is ~1 nm 3.5 µf/cm 2 accumulation capacitance at 1MHz ~1X10 12 /cm 2 -ev D it near midgap. Gate leakage < 1 A/cm 2 up V G =2 V (V. Chobpattana, et al., Scaled ZrO2 dielectrics for InGaAs gate stack with low interface trap densities, APL 2014) 6

7 Off-state leakage and S/D spacers Current Density (ma/ m) g m (ms/ m) Small S/D contact pitch MOS-HEMT with large contact pitch Band-band tunneling impact ionization L g = 18 nm V DS = 0.1, 0.5 V Gate Bias (V) Large lateral spacer low leakage, good short channel immunity Large lateral spacer large S/D pitch 7 L g =35 nm D-H. Kim, IEDM 2012

8 Vertical Spacers reduced off-state leakage SS min (mv/dec) SS min (mv/dec) DIBL (mv/v) Current Density (ma/ m) Spacer thickness 2 nm 7 nm 12 nm Open: V DS = 0.1 V Solid: V DS = 0.5 V Larger spacer 8 Spacer better short channel effect at short 60 and long channels / m) Spacer thickness 2 nm 7 nm 12 nm Open: V DS = 0.1 V Solid: V DS = 0.5 V Gate Length ( m) Gate Length ( m) 2 nm Spacer thickness 2 nm 7 nm 12 nm V DS = 0.1 to 0.7 V at 1 A/ m 0.2 V increment nm 0.0Gate 0.2 length 0.4 ( m) nm 7 nm 12 nm Gate (S. Lee, et al., EDL, June 2014)

9 Cross-sectional STEM image Courtesy of S. Kraemer (UCSB) 9 *Heavy elements look brighter

10 Current Density (ma/ m) Gate Leakage (A/cm 2 ) I-V characteristics for long channel device (L g = 1 µm) Dot : Reverse Sweep Solid: Forward Sweep L g = 1 m SS min ~ 61 mv/dec. (at V DS = 0.1 V) SS min ~ 63 mv/dec. (at V DS = 0.5 V) Gate Bias (V) 61 mv/dec Subthreshold swing at V DS =0.1 V Negligible hysteresis <1 A/cm 2 gate leakage at measured bias range

11 Current Density (ma/ m) Current Density (ma/ m) g m (ms/ m) Current Density (ma/ m) I-V characteristics for short channel devices ( L g = 25 nm) L g = 25 nm I on = 500 A/ m (at I =100 na/ m, V =0.5 V) off DD V DS = 0.1 to 0.7 V 0.2 V increment V GS = -0.4 V to 0.7 V 0.1 V increment R on = 303 Ohm- m at V GS = 0.7 V L SD = 140 nm L g = 25 nm Gate Bias (V) L g = 25 nm V DS = 0.1 to 0.7 V 0.2 V increment DIBL = 76 mv/v V T = -85 mv at 1 A/ m SS min ~ 72 mv/dec. (at V = 0.1 V) DS SS min ~ 77 mv/dec. (at V = 0.5 V) DS Gate Bias (V) ~2.4 ms/μm Peak g m at V DS =0.5 V ~300 Ohm-µm on-resistance at V GS =0.7 V 77 mv/dec Subthreshold Swing at V DS =0.5 V, 76 mv/v DIBL at 1 µa/µm 0.5 ma/µm I on at I off =100 na/µm and V DD =0.5 V 11 Drain Bias (V)

12 On-Resistance (Ohm- m) Resistance (Ohm- m) Source/drain series resistance Rcontact R N+S/D Raccess Rspacer Rballistic R on = m (+/ m) (extrpolated at zero L g ) at V GS = 0.7 V Gate Length ( m) Y = *X c = m 2 R N+SD = 85 - m Ti/Pd/Au Gap 60 nm N+ InGaAs (regrown contact layer) 5 nm Intrinsic InGaAs (Capping layer) 0 Channel Gap ( m) R contact [Ohm-µm] R N+ S/D [Ohm-µm] R spacer [Ohm-µm] R ballistic [Ohm-µm] R on at zero L g [Ohm-µm] for both source and drain sides From TLM measurement for N+S/D, R N+S/D sheet = 25 ohm/sq, ρ c = ~5.3 ohm-μm 2 R spacer is estimated to be ~35 ohm-μm for both sides 12

13 SS min (mv/dec) Current Density (ma/ m) Performance comparison: 2.5 nm VS 5.0 nm-thick channel nm InAs 2.5 nm InAs Open: V DS = 0.1 V Solid: V DS = 0.5 V Gate Length ( m) nm InAs SS ~ 60 mv/dec at V DS =0.1 V L g =500 nm I G I D Gate Bias (V) 5.0 nm InAs SS ~ 64 mv/dec at V DS =0.1 V L g =500 nm I D I G Gate Bias (V) Better SS at all gate length scale: Better electrostatics, reduced BTBT ~1:10 reduction in minimum off-state leakage ~5:1 increase in gate leakage increased eigenstate 13

14 Gate Capacitance ( F/cm 2 ) Carrier Density (/cm 2 ) x Peak g m (ms/ m) eff (cm 2 /s-v) Performance comparison: 2.5 nm VS 5.0 nm-thick channel V DS = 0.5 V InAs channel thickness 2.5 nm 5.0 nm Freq: 200kHz Gate Length ( m) W/L= 25 m/21 m C ox = 4.2 F/cm 2 EOT= 0.8 nm 2.5 nm InAs 5.0 nm InAs Gate Bias (V) Energy (ev) nm InAs 5.0 nm InAs Carrier Density (/cm 2 ) ~1.25 nm ~2.5 nm E F E Position (nm) E F E nm thick 5 nm thick x Position (nm) 1D-Possion Schrodinger solver (coded by W. Frensley, UT Dallas) 14

15 SS min (mv/dec.) SS and DIBL vs. L g (Benchmarking) DIBL (mv/v) 120 Solid: V DS = 0.5 V [2] Open: V DS = 0.1 V [4] 110 [3] [7] [1] [6] [5] This work Gate Length ( m) [1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013 [5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009 <80 mv/dec at sub-30 nm L g and V DS =0.5 V Record low subtheshold swing among any reported III-V FETs. Lowest DIBL among planar-type III-V FETs. 140 Planar [6] 120 [3] 100 [1] Tri-gate or GAA 80 [2] [4] 60 [7] This work Gate Length (nm) 15

16 Peak g m (ms/ m) Peak g m and I on at fixed I off vs. L g (Benchmarking) I on (ma/ m) V DS = 0.5 V 1.2 [5] [6] 0.8 [7] [3] 0.4 [4] [1] This work Gate Length ( m) This work V DD = 0.5 V I off = 100 na/ m This work J. Lin, IEDM2013 T. Kim, IEDM2013 Intel, IEDM2011 Intel, IEDM2009 J. Gu, IEDM2012 D. Kim, IEDM2012 [1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013 [5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM Gate Length (nm) >2.4 ms/µm peak g m at V DS =0.5 V and sub-30 nm L g. Highest I on at I off =100 na/µm and V DD =0.5 V 0.5 ma/µm I on at sub-30 nm L g 16

17 Benchmark with 22 nm node Si Fin- and nanowire FET Intel 22 nm Si FinFET IBM 22 nm nanowire FET S. Bangsaruntip et al., IEDM 2013 Jan, IEDM 2012 Intel 22 nm FinFETs (HP) : ~0.5 ma/µm V GS =0.5 V, V DS =0.75 V IBM 22 nm nanowire : ~0.4 V GS =0.5 V, V DS =0.5 V Comparable performance with state-of-the-art Si-FinFETs (nanowire). 17

18 Conclusion Developed vertical spacer to reduce off-state leakage and to improve short channel effect. Integrated sub-1 nm EOT ZrO 2 high-k with low D it Obtained 61 mv/dec at V DS =0.1 V and 1 μm-l g. Obtained 0.5 ma/μm at I off =100 na/μm and V DD =0.5 V (best reported I on among any reported III-V MOSFETs) Achieved comparable I on to state-of-art multi-gate Si-FETs 18

19 Acknowledgment Thanks for your attention! Questions? This research was supported by the SRC Non-classical CMOS Research Center (Task ). A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR *sanghoon_lee@ece.ucsb.edu 19