Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures

Transcription

1 Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Chenming Hu and Je Min Park Univ. of California, Berkeley -1-

2 Outline Introduction Background and Motivation MOSFETs with Vacuum-Spacer Vacuum-Corridor Interconnects -2-

3 Reducing Capacitance is Important for Speed Delay CV I Q I T OX (Å) T ox (C ) 10 classic scaling V DD (V) V dd (V) 1 V TH (V) V t (V) Gate Length, Lgate (um) B. Meyerson, IBM, Semico Conf., January

4 Reducing Capacitance is Good for Swiching Energy and Noise 1000 Energy CV 2 Crosstalk Noise C m Power (W/cm 2 ) C m Gate Length (μm) B. Meyerson, IBM, Semico Conf., January 2004 Metal Lines -4-

5 Outline Introduction MOSFETs with Vacuum-Spacer Structure, benefits, process Self-Aligned Contact (SAC) MOSFET Vacuum-Corridor Interconnects Future Works -5-

6 1996 Air-Gap Structure There is only 6% inverter speed improvement The fringing capacitance is much smaller than other gate capacitances Relatively small portion of air-gap (15nm) Air-gap P M. Togo, VLSI

7 Gate Capacitances Gate-channel capacitance Gate overlap capacitance Junction/Diffusion capacitance Fringing capacitance Gate-to-Contact capacitance Gate Contact Source Drain -7-

8 Vertical Scale Down is Difficult Gate shape Gate Length Ideal Scaling Gate Height Real Scale Down -8-

9 C GC becomes the Dominant Capacitance in Transistor C GOX : Gate Oxide Capacitance C GC : Gate-to-Contact Capacitance C GOX» C GC C GOX < C GC Contact Gate Scale Down -9-

10 I DS -V GS Characteristics are Same A vacuum spacer transistor is compared with an oxide spacer transistor at 20nm gate length Oxide Spacer Contact 1.0E E-03 V DS =1.0V 1.0E-04 Gate Vacuum Spacer IDS(A/um) 1.0E E E E-08 Conventional Oxide Spacer Air Spacer 1.0E V GS (V) -10-

11 Gate Capacitances and switching Charges are Reduced V DS = 1V CGATE(fF/um 2 ) Oxide Spacer Air Spacer Oxide Spacer Vacuum Spacer Q GATE fc/um V GS (V) Energy CV 2 = QV -11-

12 3D Mixed-Mode Device Simulation Extract Propagation Delay Inverter Switching Energy : V DD I DD dt V IN V DD V OUT I DD Miller Capacitances C L -12-

13 Vacuum Spacer CMOS is faster than Oxide Spacer CMOS Oxide Spacer Vacuum Spacer Voltage (V) ps 6.1ps E-11 2E-11 3E-11 4E-11 5E-1 Time (s) -13-

14 Gate Spacer Comparison Air spacer is compared with nitride spacer and oxide spacer Contact Nitride Spacer Oxide Spacer Vacuum Spacer I ON ma/um I OFF na/um Nitride Spacer Inverter Delay, ps 6.9 (1.12) 6.15 (1) 4.7 (0.76) Inverter switching energy, fj 29.5 (1.22) 24.2 (1) 18.1 (0.75) -14-

15 The Benefits of Vacuum Spacer in Future Linear Contact are Greater Future contact may be linear, not circular Nitride Spacer Oxide Spacer Air Spacer Circular Contact Inverter Delay, ps Circular Linear 6.9 (1) 5.96 (1) 6.15 (0.89) 4.64 (0.78) 4.7 (0.68) 3.28 (0.55) Linear Contact Inverter switching energy, fj Circular Linear 29.5 (1) 37.2 (1) 24.2 (0.82) 29.8 (0.80) 18.1 (0.61) 20.1 (0.54) -15-

16 Process Flow ILD1 Mask Oxide Sacrificial Spacer (a) After S/D formation (b) ILD deposition (c) Chemical Mechanical Polishing (d) Sacrificial spacer removal ILD2 Air Spacer Sacrificial spacer Oxide Gate Source/Drain Substrate (e) ILD2 deposition -16- Jemin Park et. al., Air Spacer MOSFET Technology for 20nm Node and Beyond, IEEE ICSICT, Oct. 2008, p53-56

17 Fabrication in Progress Thickness (A) SOI Thinning Before SOI Thinning After SOI Thinning #1 #2 #3 #4 #5 #6 #7 avg Wafer number Oxidation condition (Tystar2): 900, O sccm, oxidation 600min, post anneal 20min T C B L R TL TR BL BR AVG Tafter Cafter Bafter Lafter Rafter Tlafter Trafter Blafter Brafter AVGafter Alignment Mark Active Patterning -17-

18 Another Style of Contact Design, Self-Aligned Contact Conventional Contact Gate Contact Perfect Alignment Self-Aligned Contact Gate Contact Misaligned WSi2 Poly-Si Contact Silicon Nitride -18-

19 SRAM size can be reduced with SAC Intel 45nm SRAM Cell Contact Imaginary Design using SAC Contact Gate Active Intel Tech. Journal, Vol. 12, 2008 Design Rule : F Cell Width : 10F Cell Height : 5F Cell Area : 50F 2 Design Rule : F Cell Width : 10F Cell Height : 3.5F Cell Area : 35F 2-19-

20 Proposed Process Procedure of SAC with Vacuum Spacer (a) Gate stack deposition (b) Gate etch and sidewall oxidation (c) S/D and spacer formation (d) ILD deposition and CMP Air Spacer Contact Nitride Oxide (e) SAC etch and (f) CMP and remove contact plug deposition nitride material (g) ILD2 deposition Jemin Park et. al., Air-Spacer Self-Aligned Contact MOSFET for Future Dense Memories, IEEE SISPAD, Japan, Sep. 2008, p53-56 Gate Source/Drain Substrate -20-

21 Gate Last Process with SAC and Vacuum Spacer (a) After CMP Process (b) Remove sacrificial gate and form gate stack (c) Top sacrificial spacer formation (d) ILD deposition and SAC formation Air Spacer Substrate GOX Source/Drain Gate Sacrificial Spacer Contact Sacrificial Gate ILD (e) Remove sacrificial spacers (f) ILD2 Deposition Jemin Park et. al., Gate Last MOSFET with Air Spacer and Self-Aligned Contacts for Dense Memories, IEEE VLSI-TSA, Taiwan, Apr. 2009, p

22 The Case for Vacuum Spacer SAC SAC MOSFET with vacuum spacer is denser, faster, lower energy than a conventional MOSFET, 20nm. Air Oxide Spacer Nitride SAC Air SAC I ON ma/um Oxide Nitride I OFF na/um Inverter Delay, ps 6.15 (1) (1.93) 5.05 (0.82) Inverter switching energy, fj 24.2 (1) 44.8 (1.85) 18.8 (0.78) Relative Area

23 Vaccum spacer scaling effect Benefits increase with scaling 14 SAC with Nitride Spacer Delay Time (ps) SAC with Air Spacer Gate Length (nm) Improvement (%) Switching Energy (fj) Gate Length (nm) Improvement (%) -23-

24 Outline Introduction MOSFETs with Vacuum-Spacer Vacuum-Corridor Interconnects The Proposed Process of Air-Corridor The Characteristics of Air-Corridor Future Works -24-

25 Previous Air-Gap Structures An air gap is located only between metals -25-

26 Proposed Vacuum-Corridor structures C TOTAL Delay, C M Crosstalk Noise C M C O C O C M Dielectric Beam Etch Stop layer Metal Overlap Capacitance : C O Mutual Capacitance : C M Total Capacitance : C TOTAL -26-

27 Process Flow I Stopper Sacrificial Material IMD Metal (a) Via Etch (b) Line Etch (c) Metal depo & CMP (d) Etch Stopper & IMD (e) Dielectric beam Spacer Formation Jemin Park et. al., VMIC, Fremont CA, Oct. 2008, p (f) Sacrificial material depo & CMP -27-

28 Process Procedure II Stopper Sacrificial Material IMD Metal (g) Metal 2 Process (h) Metal 3 process (i) Removal all Sacrificial Material Jemin Park et. al., VMIC, Fremont CA, Oct. 2008, p

29 ITRS Key Parameters of Each Generation Metal Width 59nm 40nm 28nm 20nm Metal Space 59nm 40nm 28nm 20nm Metal A/R Metal Thick 1062Å 720Å 532Å 400Å Required Bulk Dielectric Constant Stopper Layer Thick 10nm 10nm 5nm 5nm IMD Thick (Metal + Via Height) Beam Dielectric Constant for Air-Corridor 2124Å 1440Å 1064Å 800Å ITRS spec Assumption for simulation -29-

30 Capacitances vs. Vacuum Percentage Metal Line Dielectric Beam 20% of vacuum percentage Capacitance (af/um) C TOTAL,con C Mutual,con Total Capacitance Mutual Capacitance Air percentage (%) Thicker Beam Dielectric 80% of vacuum percentage -30-

31 Insensitive to via height Total Capacitance (af/um) Conventional Structure Air-Corridor Structure Via Height (A) Mutual Capacitance (af/um) Conventional Structure Air-Corridor Structure Via Height (A) -31-

32 Vacuum-Corridor has less RC delay and higher CMP margin Relative Delay vs. Metal Height 5 60 Relative RC delay Conventional Structure Air-Corridor Structure Metal Height (A) Improvement (%) -32-

33 The Effective k of Vacuum-Corridor Interconnects Beam Dielectric Constant No Solution No Solution Air Percentage (%) -33-

34 Papers and Patents PAPERS: 1. An Vacuum-Sheath Interconnect Structure for Dense Memory Je Min Park and Chenming Hu Electronics Letters, accepted and will be published on December, Air-Spacer MOSFET with Self-Aligned Contact for Future Dense Memories Je Min Park and Chenming Hu Electron Device Letters, accepted and will be published on December, Gate Last MOSFET with Air Spacer and Self-Aligned Contacts for Dense Memories Je Min Park and Chenming Hu VLSI-TSA, pp , Taiwan, Apr Air-Spacer MOSFET Technology for 20nm Node and Beyond Je Min Park and Chenming Hu ICSICT, pp53-56, China, Oct Air-Spacer Self-Aligned Contact MOSFET for Future Dense Memories Je Min Park and Chenming Hu SISPAD, pp , Japan, Sep An-Air-Corridor Interconnect Structure Je Min Park and Chenming Hu VMIC, pp , Fremont, CA., Oct PATENTS: (UC Patents Pending) 1. Transistor Speed And Power Improvements Je Min Park and Chenming Hu UC Case "Air Corridor Interconnect Structure" Je Min Park and Chenming Hu UC Case