EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

Transcription

1 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1

2 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic fabrication process 2

3 Identification of Wafer Surface Crystallization Flats can be used to denote doping and surface crystallization Dopants (impurities) for Si: n-type dopant (donor): hosphors (), Arsenic (As) p-type dopant (acceptor): Boron (B) 3

4 The Diamond Structure Materials possess diamond structure: Si, Ge 8 atoms per unit cell Any atom within the diamond structure will have 4 nearest neighboring atoms 4

5 The Zincblende Structure Difference with the diamond structure: two different types of atoms (e.g., GaAs) Each Ga atom has four nearest As neighbors and each As atom has four nearest Ga neighbors 5

6 Overview of Microelectronic Devices BJT (12.1, 12.2) Transistors (multi-junction devices) MOSFET (10.1) JFET (13.1) and diodes, resistors, capacitors, inductors Microelectronic circuits Digital circuits: mainly CMOS transistors Analog circuits: resistors, capacitors, and CMOS and BJT transistors 6

7 Structure of BJT Emitter n++ p+ n Collector Base Emitter p++ n+ p Collector Base 7

8 Operation rinciple (NN) Forward active mode Operation involves both electrons and holes, so is called bipolar Junction E-B is forward biased, so electrons from the E (emitter) to the B (base) Junction B-C is reverse biased, so minority carrier electron concentration in B region at the B-C edge is close to zero. In the B region, there is large gradient of electron (minority carrier) concentration; the electron injected from E region will diffuse across the B region into the B-C space charge region An electric field due to the B-C reverse bias will sweep the electrons to the C (collector) region The B regions must be thinner than the minority carrier diffusion length in order to make as many electrons as possible to reach the C region. 8

9 NN with Forward Active Mode Common-base connection: Circuit symbol: i C i B i E 9

10 Operation modes of BJT Mode BE junction BC junction Currents Active Forward Reverse i c = βi B Cutoff Reverse Reverse i E = i B = i C =0 Saturation Forward Forward i c < βi B Reverse active Reverse Forward i c = β R i B Analysis: Active mode: most useful bias mode when using a bipolar junction transistor as an amplifier Cutoff mode: no electron injected to the base, all currents are zero. Used as off state in digital circuits or open switch Saturation mode: used as on state in digital circuits or closed switch Reverse active mode: emitter and collector regions switch roles. Seldom used. 10

11 Basic Structure of MOSFET N 11

12 Metal-Oxide-Semiconductor (MOS) Structure 12

13 MOS Structure Under Reverse Bias Metal layer n-type inversion layer Oxide layer type - With large positive gate bias, there will be electrons at the interface between the oxide and semiconductor, which leads to formation of a thin n-type inversion layer Threshold voltage V T : applied gate voltage required to achieve the threshold inversion 13

14 Voltage-Current Relationship of NMOS (1) 14

15 CMOS Technology Complementary metal oxide semiconductor (CMOS) 15

16 Structure of JFET N-channel JFET a long channel of n-type (N-channel) or p-type (p-channel) semiconductor. Two ohmic contacts with each at one end of the channel: the source and the drain The gate (control) terminal has doping opposite to that of the channel, so there is a N junction at the interface between the junction and the channel. The contact from gate to outside is also ohmic. 16

17 Function of JFET The two gate terminals are tied together to form single gate connection; the source terminal is grounded The flow of electric charge through a N JFET is controlled by constricting the current-carrying channel; the width of the channel is controlled by the gate voltage through varying the depletion region at the N junction at the interface between the gate and the channel The current also depends on the electric field between source and drain 17

18 Other Features of N JFET JFET is unipolar device since only majority carriers transport in the channel The source and drain region are interchangeable N-channel devices have greater conductivity than p-channel types, since electrons have higher mobility than holes The gate current is approximately zero since the N junction is reverse biased Symbols of JFET (arrow represents the polarity of the N junction) 18

19 Comparisons of Transistors BJT MOSFET JFET Structure NN: n ++ p + n N: p ++ n + p n(p)-type inversion layer structure as channel from S to D Inversed biased N junction between the gate and channel from S to D Current transport Diffusion Drift Drift Carriers involved in current transport Bipolar: electrons and holes Unipolar NMOS: electrons MOS: holes Unipolar: N-channel: electrons -channel: holes Current at terminals I C =βi B = (1/α) I E (Forward active mode) I C =f(v BE, V BC ) I G =0 I D =f(v GS, V DS ) I G 0 I D =f(v GS, V DS ) 19

20 Comparisons of Transistors (Cont d) BJT MOSFET JFET Symbols NN N NMOS MOS N-channel -channel Applications Current-controlled current amplifier Switch for digital signal Discrete circuits Voltage-controlled current amplifier Switch for digital signal IC circuits Voltage-controlled current amplifier Switch for digital signal IC circuits 20

21 Typical N-well CMOS Manufacturing rocess Step #1: Oxidation (a) -type substrate cleaning SiO 2 (b) Oxidation After wafer cleaning, SiO 2 is deposited by wet oxidation and dry oxidation 21

22 Step #2: hotolithography Defining N-well R (a) Deposit photoresist (R) (c) Develop R UV-light Mask #1 (b) Exposure under the UV light (d) Etch SiO 2 and remove R 22

23 Step #3: Diffusion to Form N-well (a) N-well predeposition n-well (b) N-well drive in The above diffusion process could also be replaced by ion implantation. 23

24 Step #4: Formation of Gate Structure n-well (a) Strip off remaining oxide using hydrogen fluoride (HF) n-well olysilicon Thin gate oxide (b) Deposit thin layer of gate oxide and polysilicon. n-well (c) attern poly-si and oxide layers using photolithography process. 24

25 Step #5: Formation of N-type Diffusion Regions n-well (a) Deposit oxide layer to pattern the diffusion regions n+ n+ n+ n-well (b) attern oxide layer to define the n-type diffusion regions and create diffusion regions n+ n+ n+ n-well (c) Strip off the oxide layer 25

26 Step #6: Formation of -type Diffusion Regions p+ n+ n+ p+ p+ n+ n-well Similar process as Step #5 is used to create p-type diffusion regions 26

27 Step #7: Formation of Insulation Layer with Metal Contacts p+ n+ n+ p+ p+ n+ n-well Nitride (a) Deposit nitride layer p+ n+ n+ p+ p+ n+ n-well (b) Etch nitride layer to leave metal contact cuts 27

28 Step #8: Formation of Metal Contacts Metal p+ n+ n+ p+ p+ n+ (a) Deposit metal layer n-well p+ n+ n+ p+ p+ n+ n-well (b) attern metal layer and form metal contacts 28

29 Summary of Fabrication rocesses Oxidation Diffusion Ion implantation hotolithography Etching Thin film deposition (non-metal and metal layers) 29