Lecture #29. Moore s Law

Transcription

1 Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday at 5/8 Prof. King & TAs will hold office hours through 5/22 OUTLINE MOSFET scaling (reprise) SOI technology MOS memory devices EE130 Lecture 29, Slide Moore s Law # transistors/chip doubles every 1.5 to 2 years Heading toward 1 billion transistors in 2007 Pentium 4 Processor Pentium III Processor Pentium II Processor Pentium Processor 486 DX Processor 386 Processor ,000,000, ,000,000 10,000,000 1,000, ,000 10,000 1,000 EE130 Lecture 29, Slide 2

2 Intrinsic Gate Delay (C gate V DD / I Dsat ) V DD =0.75V 0.85V EE130 Lecture 29, Slide 3 Silicon on Insulator (SOI) Technology T SOI Transistors are fabricated in a thin single-crystal Si layer on top of an electrically insulating layer of SiO 2 Simpler device isolation savings in circuit layout area Low junction capacitances faster circuit operation Better soft-error immunity No body effect Higher cost EE130 Lecture 29, Slide 4

3 Partially Depleted SOI (PD-SOI) T SOI > W dm, where W dm = 2ε s(2ψ B ) qn body Floating body effect (history dependent): 1. When a PD-SOI NMOSFET is in the ON state, at moderate-to-high V DS, holes are generated via impact ionization near the drain 2. Holes are swept into the neutral body, collecting at the source junction 3. The body-source pn junction is forward biased 4. V T is lowered I Dsat increases kink in output I D vs. V DS curve EE130 Lecture 29, Slide 5 Fully Depleted SOI (FD-SOI) T SOI < W dm, where W dm = 2ε s(2ψ B) qn body No floating body effect! V T is sensitive to SOI film thickness Poorer control of short-channel effects due to fringing electric field from drain Elevated S/D contact structure needed to reduce R S, R D Gate SOI SiO 2 EE130 Lecture 29, Slide 6 Silicon

4 Volatile Semiconductor Memory Static random access memory (SRAM) Dynamic random access memory (DRAM) Non-Volatile Mask programmed ROM Programmable Read-Only Memory (PROM) Electrically programmable ROM (EPROM) Electrically erasable PROM (E 2 PROM) Flash EPROM EE130 Lecture 29, Slide 7 6-Transistor CMOS SRAM Cell WL ~1 ns read time <10 ns write time V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL EE130 Lecture 29, Slide 8

5 6T-SRAM: Layout Modern processes can fit a 6T SRAM cell in ~1.0µm 2 M2 M4 V DD Q Q M1 M3 M5 M6 GND WL BL BL EE130 Lecture 29, Slide 9 SRAM Scaling Challenges Low standby power low OFF current (e.g. 1 pa/cell) large V T is required Soft error immunity EE130 Lecture 29, Slide 10

6 WL BL 1-Transistor DRAM Cell WL Write "1" Read "1" ~10 ns read time ~100 ns write time M1 C S X GND V DD V T C BL BL V DD /2 V DD sensing V DD/2 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V BL V PRE = ( V BIT V PRE ) C S + C BL Voltage swing is small; typically around 250 mv. EE130 Lecture 29, Slide 11 DRAM Cell Structure Desired characteristics: low power consumption long retention time fast access time soft error immunity Capacitor 25fF/cell is required for sensing signal margin and retention time Transistor Gate Body EE130 Lecture 29, Slide 12

7 Advanced DRAM Capacitor Structures Trench Capacitor Stacked Capacitor Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Transfer gate Isolation Storage electrode EE130 Lecture 29, Slide 13 DRAM Scaling Challenge Long retention time low OFF current (~1 fa) large V T is required Fast access time high ON current (~100 µa) large (V GS -V T ) is required => V DD cannot be scaled down aggressively, for low power consumption Possible charge leakage paths shown here: Gate (WL) Capacitor 4 EE130 Lecture 29, Slide STI 2

8 Flash EPROM Cell Structure N+ Control Gate Inter-poly Oxide Floating gate Tunnel Oxide N+ Tunnel oxide: 8 nm thermal oxide Floating gate: 100 nm N+ poly-si Inter-poly oxide: 16 nm CVD oxide or Oxide/Nitride/Oxide stack To program this device, electrons are injected from the channel inversion layer into the floating gate through the tunnel oxide. The inter-poly oxide is thick, to prevent electrons from tunneling through it. EE130 Lecture 29, Slide 15 Program by Hot Electron Injection +1 FG +5V 3.15eV A channel Tunnel oxide Floating gate Electrons are accelerated by the lateral E-field and gain enough kinetic energy at point A (near the drain) to surmount the potential barrier. Because of the control-gate bias, electrons are injected into the floating gate. EE130 Lecture 29, Slide 16

9 Program by Fowler-Nordheim Tunneling +18V 3.15eV FG A channel Tunnel oxide Floating gate For a sufficiently high control-gate bias, electrons can tunnel from the channel inversion layer into the floating gate. EE130 Lecture 29, Slide 17-18V Erase Operation 3.15eV channel Tunnel oxide Floating gate Under a large negative control-gate bias, electrons tunnel out of the floating gate into the substrate. EE130 Lecture 29, Slide 18

10 Two V T states: Sensing the Stored Data (1) Programmed state V T =V T2 =5V, I DS =0 V R =3V I DS V DS =2V 50uA Erased Programmed 0A V T1 V R V T2 V CG (2) Erased state V T =V T1 =1V, I DS =50 ua V R =3V V DS =2V EE130 Lecture 29, Slide 19 NOR Flash Memory Architecture Each memory cell can be addressed individually by its word line (gate) and bit line (drain) EE130 Lecture 29, Slide 20

11 NAND Flash Memory Architecture For each bit line, 16 or 32 cells are connected, with one select transistor at each end of the bit line. Programmed V T > 0 V Erased V T < 0 V The source/drain region between each two adjacent cells are shared high density EE130 Lecture 29, Slide 21 NOR vs. NAND Architecture NOR NAND Chip Density Medium (64MB) Very high (2GB) Programming Hot electron injection F-N tunneling mechanism Programming speed 1us ~10us 1ms Erasing speed ms byte/block erase ms block erase Random access Yes No Application Code storage Data storage Vendor Intel, AMD SanDisk, Toshiba, Samsung EE130 Lecture 29, Slide 22

12 Flash E 2 PROM Scaling Challenges To achieve fast programming speed and low voltage operation, the tunnel oxide thickness must be scaled down. Defects in the tunnel oxide reduce the retention time and thereby limit the tunnel oxide scaling, however. Today >8nm tunnel oxide is used in commercial flash products. EE130 Lecture 29, Slide 23 Semiconductor Memory Trends Capacity increases 4X every 3-4 years Today: 1 Gb DRAM 512 MB SRAM (2MB on-chip cache SRAM) 1 Gb flash E 2 PROM EE130 Lecture 29, Slide 24