Sub-20nm Novel Silicon based transistors

Transcription

1 Sub-2nm Novel licon based transistors Yu-Lin Chao, Venkaragirish N., Ritesh Jhaveri, Ahmet Tura, and Jason C. S. Woo Department of Electrical Engineering, University of California, Los Angeles Aggressive MOSFET scaling faces the challenges of limited Ion/Ioff ratio and severe short channel effects. To overcome these problems, new device configurations made feasible by small dimensions and new materials need to be explored. In this paper, novel devices incorporating silicon and germanium are presented. These silicon and germanium based asymmetric source injection devices with superior performance have the potential to alleviate the scaling challenges for sub-25nm nodes. 1. Schottky Barrier MOSFET Schottky barrier MOSFETs which use fully silicided source/drain junctions have been proposed for future veryshort-channel devices. The major advantage is the formation of ultra shallow junctions with very low resistively. In this abstract, a novel asymmetric Schottky Tunneling Source MOSFET is introduced. The operating principle of the STS MOSFET utilizes the concept of gate controlled Schottky barrier tunneling between a metal and a semiconductor. Fig. 1 shows the band diagram along the surface of the channel region at different gate voltages for a Schottky source with a barrier height (φ b ) of.45ev. When the gate voltage is sufficiently low the tunneling distance of the Schottky junction is high as well as the number of states that electrons can tunnel into is small. Hence the current injection is limited by the tunneling resistance only. As the gate voltage increases, the tunneling distance reduces and the number of states the electrons in the metal source can tunnel into increases thereby reducing the tunneling resistance. Fig 2a shows that as gate oxide thickness reduces, there is a marked improvement in STS MOSFET subthreshold characteristics as well as I ON. A sub-threshold swing of ~13mV/dec is obtained for EOT = 2Å and ~7mV/dec is obtained for EOT = 5Å. This suggests that the sub-threshold swing is a strong function of t OX as opposed to diffusion barrier transport. However, the sub-threshold swing obtained due to gate controlled tunneling is always degraded as compared to best possible diffusion limited sub-threshold swing (~6mV/dec at room temperature); even though STS has excellent DIBL and V TH roll-off characteristics. To further improve the performance of STS transistor, Schottky FETs with asymmetric source/drain pocket is proposed. Fig 2b shows that as the source pocket is made n-type with increasing dopant density, the tunneling distance (and therefore tunneling resistance) reduces for a given gate voltage and the threshold voltage also reduces. But, the sub-surface conduction goes up thereby increasing the off current. However, when the pocket is made p-type, a region of high threshold is created near the source. This reduces the subsurface conduction considerably resulting in low I OFF. I ON on the other hand is not degraded since the band-bending increases due to the p-pocket. Therefore, the tunneling width remains about the same as conventional STS transistor. The n + pocket on the drain side forms a low resistance contact between the channel and the drain, eliminating the potential drop at the drain side due to the presence of a Schottky barrier. Figure 1 Conduction Band Edge profile along the channel for different gate voltages. φ b =.45eV. I D (μa/μm) 1.x1 3 1.x1 2 1.x1 1 1.x1 1.x1-1 1.x1-2 1.x1-3 1.x1-4 t OX = 2Å 5Å 1Å 2Å φ b =.45eV V D =.1V V D = 1.V x1 2 1.x1 1 φ b =.45eV t 1.x1 OX = 5Å 1.x1-1 1.x1-2 1.x1-3 1.x1-4 1.x1-5 n type pocket (1-8X1 18 ) cm -3 p type pocket (1-8X1 18 ) cm -3 1.x V G (V) 2. Tunnel Source MOSFET To further improve the I ON /I OFF ratio, we propose the Tunnel Source (P + N + tunnel diode) MOSFET [3]. The device structure of the novel asymmetric MOSFET is shown in Fig. 3. The gate electrode controls the source-to-channel tunneling current by modulating the band-alignment between the valence band of the P + tunneling source and the conduction band of the channel (thus modulating the availability of density of states for tunneling) and modulating the tunneling width (Fig 4). I D (μa/μm) V G (V) Figure 2 (a) I D -V G characteristics of devices with different gate oxide thicknesses for a given φ b of.45ev. N BULK = 1X1 17 cm -3. (b) I D -V G characteristics with different pocket doping. N BULK = 1X1 17 cm -3, t SI = 6nm and V D =.1V.

2 Source T si T BOX V S (fixed at V) N AP N D W Fully Depleted N + layer V G (varied from to 1) N A L channel P + Buried Oxide N G N DD T OX Figure 3 Device structure of the novel PNPN MOSFET Conduction Band (a) Valence Band Gate P + P N + Drain Conduction Band (b) Valence Band V D (varied from to 1) Figure 4. Band Diagram along the channel along section S in Fig. 3. (a) V G < V TH (b) V G > V TH. Detailed simulations show that the optimized novel PNPN MOSFET exhibits a steep sub-threshold slope (<<6mv/dec) (Fig 5a) with negligible DIBL. This is due to the fact that the overlap of the available density of states changes abruptly from zero to a finite value along with a reduction in tunneling width as the gate voltage increases from to V TH. nce the subthreshold behavior is determined by the tunneling source junction, DIBL is significantly reduced. Fig. 5b shows the I D - V D characteristics for the tunnel source MOSFET and a conventional SOI MOSFET. In the above threshold regime, the resistance of the tunneling junction is negligible for the PNPN MOSFET resulting in a current characteristic similar to a conventional SOI transistor. The threshold voltage (V TH ) is defined as the gate voltage at which the channel conduction band overlaps with the source valence band. Therefore, for the same V G -V TH, the drive current is larger (band bending > 2 φ b ) for the PNPN MOSFET. I D (µa/µm) 1.x1 3 1.x1 2 V D = 1 V 1.x1 1 1.x1 1.x1-1 1.x1-2 1.x1-3 V D =.1 V 1.x1-4 1.x1-5 1.x1-6 1.x1-7 1.x1-8 1.x V G (V) I D (µa/µm) S 55 5 V TH =.325 V V G = 1 V V V 25.7 V V V.4 V V D (V) Figure 5 (a) Subthreshold Characteristics of a Tunnel Source FET. (b) I D -V D characteristics for different V G for the Tunnel Source FET (dotted) and conventional MOSFET (solid) 3. Tunneling transistors on GeOI Germanium has regained attention for its low field high electron and hole mobilities which are beneficial for carrier transport in nanoscale devices. In addition, due to its smaller bandgap and therefore smaller tunneling width, Ge is the material of choice for both the Schottky FET and the Tunnel Source FET. To better control short channel effects and junction leakage current and to make germanium acceptable in current silicon production line, germanium-on-insulator (GeOI) is preferred. GeOI substrates can be obtained by wafer bonding and Smart-Cut TM techniques. A successfully transferred germanium on oxidized silicon wafer is shown in Fig. 6. The fabricated GeOI substrate has large amounts of vacancies which are the major diffusion vehicles in germanium. The electrical concentrations in bulk germanium and GeOI are then determined by the Fermi level dependency of dopants (Fig. 7a). Boron yields identical active concentration in two substrates, whereas phosphorous shows lower active level in GeOI due to faster diffusion assisted by charged vacancies, and this may affect scalability of germanium nmosfets. Another challenge of Ge devices is the quality of gate stack. A stable metal gate electrode against the selection of gate dielectrics is essential. In our study, Mo/germanium oxynitride gate stack is found to be thermally stable up to 4 C with interface charge density in the orders of 1 12 /cm 2, as shown in Fig. 7b. A further reduction of the charge density is still needed. (a) Figure 6 XTEM of a GOI sample Figure 7 (a) Electrical concentrations of n- and p-type dopants in bulk Ge and GeOI (b) C-V curves of Mo/germanium oxynitride gate stack before and after annealing. 4. References [1] Moongyu Jang et al, IEEE Transactions on Nanotechnology, Vol.2, No. 4, pp 25-29, 23. [2] Kazuya Matsuzawa et al, IEEE Transactions on Electron Devices, Vol. 47, No. 1, pp 13-18, 2. [3] N. V. Girish, Ritesh Jhaveri and Jason C. S. Woo, IEEE 24 licon Nanoelectronics Workshop, 24, pp (b)

3 Outline Sub-2nm Novel licon based transistors Jason C. S. Woo University of California, Los Angeles Motivation for sub-25nm novel device concepts GeOI Devices Schottky Transistors Tunnel Source (PNPN)MOSFET CMOS Research Laboratory Scaling Challenges Challenges arising due to scaling in the sub-nm regime Source/Drain-to Channel Electrostatic Coupling Channel Transport Limitation (Mobility Reduction, Velocity saturation) Parasitic Effects (Source/Drain Resistance/Capacitanc, Gate Leakage) SDE & Series Resistance Scaling Trends Gate Length or SDE Depth [nm] Lchtox Rch ( V V ) th 21 ITRS Physical Gate Length Max. Ratio of R sd to Ideal R ch SDE Junction Depth gs 1 Rsd Rsh N X sd j Year R sd / R ch,ideal [%] Scaled with L g (L ch, t ox ) Difficult to scale R sh R sd /R ch (N sd, X j ) Relative Contributions of Resistance Components S/D Series Resistance [Ωµm] NMOSFETs 5 NMOS scaled by ITRS R ov R ext R dp R csd 32 nm 53 nm 7 nm 1 nm Physical Gate Length Relative Contribution [%] 7 6 NMOS R csd R ext 2 R ov 1 R dp 32 nm 53 nm 7 nm 1 nm Physical Gate Length Assumptions : Scaled according to ITRS projection Gradual doping & midgap silicide material R csd will be a dominant component for highly scaled nanometer transistor ( R csd /R series is rising up to >> ~ 6 % for L G < 53 nm) Relative Contributions of Resistance Components S/D Series Resistance [Ωµm] PMOSFETs PMOS scaled by ITRS R ov R ext R dp R csd 32 nm 53 nm 7 nm 1 nm Physical Gate Length 32 nm 53 nm 7 nm 1 nm Physical Gate Length Relatively large R ov contribution, but still largest in R csd ( R csd /R series : ~ 6 %, R ov /R series : 2 ~ 3 % for L G < 53 nm) Relative Contribution [%] R ov R csd R ext PMOS R dp

4 Advanced S/D Engineering SOI MOSFET N sd (x) S/D Series Resistance [Ωµm] Box Profile Low-Barrier licide (Φ B =.2 ev) Box Profile Midgap licide Graded Junction Midgap licide L G = 53 nm Potential solutions for advanced S/D Engineering: R ov R ext R dp R csd Source/Drain Engineering Box-shaped highly-doped ultrashallow SDE junction (i.e., laser annealing) Schottky Barrier lowering (i.e., Er for NMOS, Pt 2 for PMOS, and lower bandgap 1-x Ge x layer) N m,dp L con licide R u,co R sw,co R u,co N m,ext Spacer Buried Oxide Gate R R Rspr,ov ac,ov sw,co R dp,sp Rext,sp R dp,sp R ext,sp R spr,ov R ac,ov N sub x Rextrinsic = 2R sd = 2 + ( Rco + Rsp Rov) R co R sp R ov Contact resistance in SOI MOSFETs Need Contacts with Low Φ B R co (Ωµm) 1 L 9 con = 5 nm t soi = 1 nm t soi = 2 nm Uniform Doping N co = 1.5E2 cm-3 R co = R u,co //R sw,co R u,co R sw,co t soi = 4 nm t sili [nm] R co (Ωµm) mulation t soi = 1 nm t soi = 4 nm L con = 5 nm L con = 2 nm Φ B =.25 ev 1 Elevated S/D SOI t sili [nm] Low SBH (Φ B =.25 ev) (ρ c = 1.27X1-8 Ωcm 2 for uniform doping) Scaling Challenges Potential Solutions Challenges arising due to scaling in the sub-subnm regime Source/Drain-to Channel Electrostatic Coupling Channel Transport Limitation (Mobility Reduction, Velocity saturation) Parasitic Effects (Source/Drain Resistance/Capacitanc, Gate Leakage) Potential Solutions Improved Device Architecture (Double/Tri-gate MOSFETS) New materials to enhance transport (Ge or Ge channel) New Gate Dielectrics to reduce gate leakage (High-K) Small φ B contacts --- Small E G Source/Drain Junctions New Materials with Higher Mobilities New Gate Stack to Reduce Tunneling New Contact Materials (Metal and Semiconductor) to reduce R co New S/D Structures (e.g. Raised S/D) for Small R S/D SOI, DG, to improve SCE

5 Alternatives? Essentially, Try to Make Scaled MOSFETs Follow Scaling Behavior of Long Channel Device Miniaturization New Device Architectures Novel Transports Incorporate QM Effects New Materials High Mobilities Bnadgap Engineering Others CMOS Research Laboratory Lateral Asymmetric Channel (LAC) MOSFET S Conventional LAC poly poly Tilt angle θ θ BF2 (NMOS) D Impurity Concentration (cm -3 ) S L gate =.12 µm D LAC: Tilt=1 o Conv LAC Lateral Position (µm) Formation of Channels in the mulated channel profiles for devices LAC and conventional structures. with same Vth from source to drain Usual tilt angle: 1 o -15 o 1.5 nm away from the O2/ interface. Lateral Asymmetric Channel MOSFETs What are the advantages? Suppression of Short Channel Effects similar to the Double Halo (DH) structures in bulk devices Higher Current Drive than DH for both Bulk and SOI devices Higher Transconductance than DH and conventional devices for bulk devices Improved Early Voltage compared to DH in bulk devices Improved low frequency Flicker Noise compared to conventional devices LAC Transistor LAC DEVICES: ANALOG PERFORMANCE E y (1 5 V/cm) 2 1 LAC DP Conventional Lateral Position y (µm) Lateral Position y (µm) LAC Devices: Higher doping near the source end High lateral electric field near the source end in channel region High average carrier drift velocity near the source end in channel region High current drive, I ds = W C ox (V gs -V th (y)-v(y))v(y) Ave Carrier Velocity (1 7 cm/s) LAC DP Conventional g m (ms/µm) LAC T ox =25Å LAC T ox =36Å Conv. T ox =25Å Conv. T ox =36Å g m /I d (V -1 ) 5.1 NMOS LAC Tox=25 Å V ds =.8V LAC Tox =36 Å Conventional, T I ds same at same Lg & T ox =25 Å ox NMOS Conventional, T ox =36Å L g (µm) L g (µm) g m is higher in SP devices g m /I d ratio is very high compared to conventional devices when biased at same current density : - due to high current drive, small Vgt is needed. Also high g m 15 1 V gt =.3V, V ds =.8V for Conv. V ds =.8V, I ds same as Conv. for SP(V gt ~.15-.3V).

6 Issues with LAC Transistors High doping near the source Lower Mobility Sharp doping profile in sub45 nm transistors Difficult Source potential (V) H -- L gate Potential profile for the HL devic e H H gate Vds=.2 V Vds=.4 V Vds=.6 V Vds=.8 V Vds=1. V p- sub Channel position (nm) L Proposed Split Gate Design Drain The work-function of the H gate is higher than that of the L gate Lateral E-Field (MV/cm).5 H-L gate H gate.3 Lg=45nm W H -W L =.3eV.1 V gt =.2V, V ds =V Vds=.8 V Channel-X (nm) Channel position (nm) An electric field peak is generated in the channel close to the source side which enhances source carrier injection into the channel ( g m ). R out can be increased due to the reduced channel-length-modulation. E X (kv/cm) H gate H - L gate Gm(mS/mm) mulation: G m and R out in scaled MOSFETs Empty Symbol: H device Solid Symbol: HL device Lg = 45 nm 75 Lg = 9 nm Lg = 13 nm Lg = 18 nm Bias current (µα/ µm) Bias current (µα/ µm) Both g m and r out can be improved by using this split gate design for different channel length considered. R out (KΩ) R out (KΩ) Lg = 45 nm Empty symbol: H gate Solid symbol: HL gate Lg = 13 nm Bias current (µα/ µm) S b -induced Work Function Shift in the Ni Gate 2.6nm Capatance (pf) 1 Ni/Oxide Capacitor, 1µm x µm Sb doped Ni 5 (1.5x1 15 cm -2 ) T ox = 2.6nm undoped Ni Gate Bias (V) Ni Gate: Gate full silicidation and no oxide degradation. Antimony implantation in the polysilicon gate reduces the Ni gate work function (~.25eV) due to the dopant segregation effect at the Ni/oxide interface. Process Flow Id-Vg and Id-Vds curves N PR LTO Oxide/Poly/LTO: Poly 4.5nm/5nm/2nm N N Poly (a) LTO (b) N Sb Ni N (c) Ni (d) N Ni Sb implant energy, dose and angle: 25KeV, 1.5x1 15 cm -2, 3 o Nitride spacer width : ~ 8nm licide conditions: 45 o C Drain current (A/ 1µm) 1E-4 1E-5 1E-6 1E-7 (Substrates are undoped) 5.m tilt-angle doped(sb) Ni gate Undoped Ni gate Lg=.6µm V DS =.1 V Undoped Ni Tilt-angle Sb -doped Ni Vg (V) Drain current (A / 1 µm) 4.m 3.m 2.m 1.m Lg=.6µm Vg=2 V Vg=1.5 V Vg =1. V Vg=.5 V Vg= V Vds (V) Improved current drive capability is observed for the Ni gate device with tilt angle S b implantation from the drain side, i.e, the split-gate device.

7 Output resistance (KΩ) 1 Output Resistance Vds = 2. V Sb-doped Ni gate un-doped Ni gate Bias current (µa/µm) At lower bias current, both devices have similar r out due to their large DIBL as a result of un-doped substrates. At higher bias current, the split-gate device has higher r out due to its less channel-length-modulation at the drain side. g m (ms/mm) Scalable? Empty Symbol: H device Solid Symbol: HL device Rout(KΩ) Lg = 45 nm Bias Current (µa/µm) Bias Current (µa/µm) Improved speed-gain performance F T (GHz) Vth= Vth= Lg=45nm I DS =1 µ A/µm Lg=45 nm Novel Materials Lsp=27.5 nm Lsp=3 nm 2 Lsp=35 nm Lsp=4 nm Empty symbol: H device Lsp=45 nm Solid symbol: H-L device Intrinsic Gain Split-gate HL MOSFETs have improved gain- frequency performance compared with conventional MOSFETs CMOS Research Laboratory GOI MOSFET Gemanium-on-Insulators Wafers Advantages of germanium - Large low field mobilities - Reduced R S/D - Large Tunneling Probilities - Possibility of optoelectronic integration Why Germanium-on-Insulators? - Germanium is expensive ($$$) and brittle. - Germanium has high dielectric constant, so worse SCE. - Help our industry peers incorporate Ge into existing production lines. How to make it? Wafer bonding and Smart-Cut TM technologies are employed to fabricate GeOI substrates. H + Ge Bonding Anneal Ge Ge

8 Gemanium-on-Insulators Wafers Germanium film remains single crystalline known from TEM diffraction pattern. As-split XTEM Bulk Ge Dopant Activation in Ge/GeOI - The difficulty of dopant activation arises from the limited solid solubilities and fast diffusion of dopants in Ge. - Rapid thermal annealing and pre-amorphization implantation (PAI) are combined to address the issues. B, 65 C P, 6 C Before RTA Before RTA Dopant Activation in Ge/GeOI GeOI - The lower level of P activation in GeOI is due to enhanced diffusion by vacancies created by hydrogen implantation. - The cause for the high level of boron concentration in GeOI is still under investigation. Gate Dielectric/Electrode in Ge Germanium oxynitride is used as gate dielectric film in our study. This film seems to exhibit low gate leakage current, but the reliability remains a concern, and more study is on going. HRTEM ~13Å Al GeON Ge (Å) Motivation Novel QM-Injection Transistos V s/db unscaled V th S I off I on V supply Higher I off and reduced I on /I off ratio Exploit novel device physics concepts made possible by nano-dimensions to achieve steep subthreshold swing and ballistic carrier transport to give high I on. V s/db Source/Drain-Substrate Junction Potential V th Threshold Voltage S Subthreshold Swing CMOS Research Laboratory

9 Assymetric Schottky Tunneling Source MOSFET Device Concept Source licide Gate Fully depleted N/P layer Drain P N + licide Buried Oxide Schottky Barrier between Fully Depleted pocket and the source silicided junction Fully licided Source/ Drain Junctions N + Region on the drain side to form an ohmic contact between drain and substrate The gate controls the tunneling through the schottky barrier on the source side by changing the tunneling width as well as the available density of states on the semiconductor side Electron Energy (ev) φ b Source Vg = V Vg = 1 V Conduction Band Valence Band Drain..5.1 Distance along the channel (μm) Band Diagram across the channel at different gate voltages (V g ) for V drain =.1 V and φ b =.55 ev a) V gate < V threshold Tunneling Distance of the schottky junction is large Number of available states on the semiconductor side is limited Subthreshold current is limited by schottky tunneling resistance b) V gate > V threshold Tunneling Distance decreases Number of available states on the semiconductor side increases Tunneling Resistance decreases and current gets limited by channel and tunneling resistance depending on certain parameters at the schottky junction Barrier Height (φb) Gate Oxide thickness (t ox ) Drain Current I d (μa/μm) 1.x1 2 1.x1 1 1.x1 1.x1-1 1.x1-2 1.x1-3 1.x1-4 1.x1-5 φ b =.25eV.45eV.65eV t ox =2Å V d =.1 V d = 1. 1.x Gate Voltage V g (V) Drain Current I d (μa/μm) 1.x1 3 1.x1 2 1.x1 1 1.x1 1.x1-1 1.x1-2 1.x1-3 1.x1-4 t ox = 2 Å 5 Å 1 Å 2 Å φ b =.45eV V d =.1 S=8mV/decade V d = Gate Voltage V g (V) N bulk = 1x1 17 cm -3 N pocket = 1x1 17 cm -3 Pocket Doping (N pocket ) to improve I ON /I OFF I d -V d curves Drain Current Id (A/µm) 1x1-4 1x1-5 1x1-6 1x1-7 1x1-8 1x1-9 1x1-1 1x x 1-12 Φ b =.45 ev t ox = 5 Å. S=9mV/decade p_1e19 p_8e18 p_4e18 p_1e18 no pocket n_1e18 n_4e18 n_8e18 n_1e Gate Voltage Vg (V) As n-type pocket doping tunneling distance (whereby reducing threshold voltage) n-type pocket doping ; subsurface conduction increases p-type doping a region with high threshold is obtained near the source This reduces subsurface conduction and I on /I off ratio considerably φ b =.45 ev t ox = 5 A O Vg = 1 V V V V Drain Voltage V d (V) Drain Current I d (μa/μm) Due to much better control of SCEs the R out at a given I D is much higher than for a conventional device. However, I on is always smaller than conventional MOSFET at same (V g V th ) at a given t ox which degrades the gm/i DS ratio This is due to a drop at the schottky junction which reduces effective drainsource voltage (V DS )

10 The Tunnel Source MOSFET A novel device structure incorporating gate controlled source injection by band-to-band tunneling Tunneling Source Transistors governed by Tunneling Probability(T t ) dependent on the Tunneling width Device Physics Enabled by small-dimensions: Quantum Mechanical Tunneling (Band-to to-band) governed by Fermi Selection Rule F V (E)* [1-F C (E)]* ]*u(e) Where u(e) =1 if there is availability of states to tunnel to; otherwise. F V (E) and F C (E) are Fermi-Dirac distribution functions for the initial (valence band) and final (conduction band) energy states. Basic Equation used for the tunneling current: Esaki Diode integral I V-C =A F V (E)*n V (E)*T t *[1-F C (E)]* ]*n C (E)* u(e)de The Tunnel Source (PNPN) MOSFET Gate controlled P + -N + tunneling junction is used as a source of electrons (Tunneling width is reduced by the fully depleted N + layer) Novel device concept based on Band-to-Band Tunneling Source Gate Drain The Tunnel Source (PNPN) MOSFET Gate controls the source-to-channel tunneling current by modulating the band-alignment between the valence band of the tunneling-source junction and the conduction band of the channel, thus modulating the availability of density of states for tunneling modulating the tunneling width (which is already made small because of the narrow and fully depleted n-pocket) P + N + P P + N + Fully Depleted N + layer Buried Oxide S Important condition for successful device operation: The n-pocket of the PNPN device needs to be narrow (<1nm) The doping of the pocket should be such that it is fully depleted The Tunnel Source MOSFET Tunneling Width Minimization Conduction Band Valence Band (a) Conduction Band (b) Valence Band For any given width W, doping needs to be less than N dmax to maintain full depletion. As W decreases, N dmax as shown. V G < V TH V G >V TH When V G < V TH, current level is small since the electrons from the P + valence band can tunnel only to the trap states When V G > V TH, electrons from the P + source valence band tunnel to empty states in the conduction band of the channel As the width W of the N- pocket decreases, the voltage drop across the tunneling junction reduces. A width of 3nm or less is needed for negligible voltage drop.

11 Small Pocket Width (W) Pocket Doping (N D ) V T =.45 V T =.35 W=1nm W=3nm N D =1x1 19 cm -3 N D =9x1 19 cm -3 V G =.9 V G =.9 V G =.8 V G =.7 N D =1.6x1 2 cm -3 V D =1V N D =1x1 2 cm -3 V G =.8 V G =.7 V G =.6 V G =.6 V G =.5 V G =.4 N D =8x1 19 cm -3 A narrow width (W 3nm) with a doping close to N dmax gives high I DS N D N dmax for good subthreshold characteristics by minimizing tunneling width. Pocket Doping (N D ): Device Performance I D (µa/µm) 1.x1 4 1.x1 3 N D =9.5x1 19 cm -3 (not fully depleted) 1.x1 2 V D =1V 1.x1 1 1.x1 N 1.x1-1 D =8.5x1 19 cm -3 (fully depleted) 1.x1-2 1.x1-3 N 1.x1-4 D =9x1 19 cm -3 (fully depleted) 1.x1-5 1.x1-6 1.x1-7 1.x1-8 1.x V G (V) N D > N dmax results in degraded sub-threshold slope. Device is no longer tunneling limited I D (µa/µm) 1.x1 3 1.x1 2 1.x1 1 1.x1 1.x1-1 1.x1-2 1.x1-3 1.x1-4 1.x1-5 1.x1-6 1.x1-7 1.x1-8 1.x1-9 V D = 1 V V D =.1 V V G (V) I D (µa/µm) 55 5 V TH =.325 V V G = 1 V 45 SOIMOSFET.9 V 4 35 TFET.8 V V 2.6 V V.4 V V D (V) Scaling behavior Summary L G =45nm L G =1nm Steep subthreshold slope (<<6mV/dec) & near infinite I on /I off ratio Higher drive current for a given V G -V TH (band bending > 2φ B ) Merits of the device High f T (small tunneling time constant and Less transit time) Small source-channel coupling Less Short Channel Effects and low DIBL Scalable as on-current controlled by the tunneling source High performance digital/analog transistors with high f T and high gain Even Higher performance using small E G Semiconductor --- Ge

12 Conclusion New Device Structures Exploiting Physical Mechanisms Made Feasible by Nanodimensions Ge has Small E G not just High mobilities Tunnel-Source Transistors Promosing Parasitics Still Need Special Attention