FinFET-based Design for Robust Nanoscale SRAM

Transcription

1 FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng Guo, Sriram Balasubramanian, Andrew Carlson, Radu Zlatanovici 1 Outline Background / Motivation FinFET-based SRAM cell designs 6-T SRAM write-ability considerations Summary 2 1

2 Challenges for Bulk-Si MOSFET Scaling The traditional approach to transistor scaling is reaching fundamental limits oxide scaling Source Shallow junctions Channel engineering L g Halo Doping Drain Issues for scaling L g to below 20 nm: Leakage SiO 2 Incommensurate gains in I ON V T variation Source Drain A. Brown et al., IEEE Trans. Nanotechnology, p. 195, Thin-Body MOSFET Structures Short-channel effects are suppressed with thin body Channel can be lightly doped higher carrier mobility T OX scaling is not needed reliability issues are assuaged Double-gate structure is most scalable (to L g <10nm) L g Source Drain T Si Buried Oxide Substrate Ultra-Thin Body (UTB) Source Drain Double- (DG) T Si 4 2

3 Circuit-Level Benefits of Thin-Body MOSFETs Steep sub-threshold swing High drive current Low parasitic capacitances negligible C junc and C depl Better intrinsic delay FO4 Inverter Delay [ps] 10 1 Bulk UTB DG 45% faster I off = 200nA/ m L gate =35nm 53% faster I off = 2nA/ m Benefits are enhanced for low-power applications 5 Double- FinFET L g Drain L g Drain T Si Source Drain Source Source Planar Double- FET (90 o rotation) Fin Height H FIN = W/2 Fin Width = T Si FinFET D. Hisamoto et al., IEDM, 1998 N. Lindert et al., IEEE Electron Device Letters, p.487, 2001 Rotation allows for self-aligned gate electrodes FinFET layout is similar to that of a planar FET 6 3

4 Bulk-Si FinFETs C.-H. Lee et al., Symp. VLSI Technology Digest, pp , 2004 FinFETs can be made on bulk-si wafers lower cost improved thermal conduction to mitigate self-heating effects integration with planar bulk-si MOSFETs is possible 7 FinFETs for Digital ICs Significant barriers to adoption of FinFET technology for general purpose logic exist: V T tuning (gate work function engineering?) lack of a standard model and design libraries but these are not issues for SRAM, which faces severe challenges for scaling beyond the hp45nm node V T variability standby power 8 4

5 Outline Background / Motivation FinFET-based SRAM cell designs Z. Guo et al., Int l Symposium on Low Power Electronics and Design, T cells 4-T cells 6-T SRAM write-ability considerations Summary 9 6-FinFET SRAM Cell Access Cell Layout NPD Load FinFET PARAMETER GATE LENGTH WL GATE-OX. THICKNESS V DD FIN WIDTH VALUE Load 22nm 11Å 15nm FIN HEIGHT BODY DOPING 30nm Access 1E16cm nm GATE WORKFUNCTION NPD BL V DD 4.75eV 1.0V BL 755 nm 1-Fin NPD: 0.36 m 2, 175mV SNM 2-Fin NPD: 0.42 m 2, 240mV SNM (36% SNM improvement w/ 17% area penalty) 10 5

6 6-T SRAM Design: bulk-si vs. FinFET Bulk-Si: cell area = 0.46 m 2 FinFET: cell area = 0.36 m 2 Read/Write Margin (mv) Read/Write Margin (mv) Cell Beta Ratio # Fins on NPD Write Margin Read Margin Write Margin Read Margin 11 Independent Operation The front and back gate electrodes can be isolated by a masked etch, to allow for separate biasing 1 is used for switching 2 is used for V T control Back-d FET: Drain 1 2 Source 12 6

7 SRAM Cell w/ Dynamic Feedback Circuit Schematic SNM is increased Soft-error immunity is enhanced! Word-line capacitance is reduced; I READ is unaffected 13 Selective Separation SEM picture of 6-FinFET SRAM cell after timed gate separation etch Access Connected s NPD Load Separated s Access Access transistor gates are selectively separated dynamic feedback 14 7

8 SRAM Cell w/ Dynamic Feedback (cont d) Cell Layout No area penalty is incurred to implement feedback Read vs. write margin trade-off is adjusted by M 15 4-T SRAM Design: bulk-si vs. FinFET 16 8

9 4-FinFET SRAM Cell SEM picture of 4-FinFET SRAM cell after gate patterning T Si = 30 nm, L g = 70 nm Access gate layer NPD fin / active layer NPD Access 17 Impact of Process Variations Comparison of SRAM SNM Distributions Mixed-mode & MC simulations: FinFET variations are due to parameter variations 3 Lg = 3 TSi = 10%L g Bulk-Si MOSFET variations are due to random dopant fluctuations only FinFET-based SRAM designs shows less variability 18 9

10 Systematic vs. Random Variations FinFET SRAM 6-T DG 1-Fin M =4.65eV Systematic variations have less impact than random variations SNM variation due to random mismatch in L g and T Si is ~1.8x more than that due to systematic variations 19 Outline Background / Motivation FinFET-based SRAM cell designs 6-T SRAM write-ability considerations A. Carlson et al., IEEE SOI Conference, 2006 Impact of dynamic feedback Improvement via separate write word line Summary 20 10

11 Measuring Write-ability C. Wann et al., IEEE VLSI-TSA, pp , 2005 Write functionality is increasingly important Scaling reduces NMOS/PMOS drive strength ratio Write-ability is more sensitive than SNM to V DD When biased as shown, the minimum current I W is a measure of write-ability I W 0 cannot write a zero 21 Dynamic Feedback Better Write-ability Nominal Iw (ua) M=4.65eV Vch (V) I W is increased at low V DD with dynamic feedback (Note: M values were selected so that SNM = V DD =0.7V) 20 VDD (V) Ich (ua) M=4.82eV Iw 22 11

12 Pull-Up (Load) Write Gating Connect one gate of each load transistor to a write wordline to assist with write Impact is complementary to that of dynamic feedback 3 CH 5 6 WWL 1 2 CL 4 Nominal Iw (ua) Ich (ua) 20 Improved lower V 0 DD Vch (V) PUWG + PGFB PUWG Conv VDD (V) No area penalty! 23 Dynamic feedback + PUWG can improve yield SNM Cell Sigma PUWG+PGFB PUWG PGFB Conv V DD (V) Iw Cell Sigma PUWG+PGFB PUWG PGFB Conv V DD (V) Projected yield is greatest when dynamic feedback and PUWG designs are combined Enables 6-sigma design at low V DD 24 12

13 Outline Background / Motivation FinFET-based SRAM cell designs 6-T SRAM write-ability considerations Summary 25 Summary The FinFET structure offers improved I ON vs. I OFF and immunity to statistical dopant fluctuations FinFETs can be fabricated alongside planar bulk-si MOSFETs with minimal added process complexity attractive for embedded SRAM application The FinFET s capability for back-gated operation can be leveraged to improve cell stability and write-ability, to enable 6-T SRAM technology scaling well beyond the hp45nm node 26 13

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