Silicon Single-Electron Devices for Logic Applications

Transcription

1 ESSDERC 02/9/25 Silicon Single-Electron Devices for Logic Applications NTT Basic Research Laboratories Yasuo Takahashi Collaborators: : Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Kenji Shiraishi, Masao Nagase, Seiji Horiguchi, Kenji Yamazaki, Hideo Namatsu, Kenji Kurihara, Katsumi Murase

2 1. Background Outline 2. Novel Fabrication Procedure for SETs (Pattern- Dependent Oxidation: PADOX) 3. Advantages of SETs made by PADOX 4. Application of SETs for Logic Circuits (Single-Electron Inverter & Adder, Multigate SET, Multiple-Valued Operation) 5. New Device (Single-Electron CCD) 6. Summary

3 Si Single-Electron Transistor Gate electrode Vg Silicon island Vd Silicon MOS Transistor Source e - Drain Gate electrode Vg Channel Vd Source Drain Tunnel Barrier Structure of Si SET Id Silicon Si single-electron transistor (SET) and MOSFET have similar structure V th Vg

4 Equivalent Circuit Gate electrode Source e - Vg Silicon island Drain Vd Tunnel capacitor Source Cs Gate Cg Cd Drain Tunnel Barrier Island Structure of Si SET Equivalent Circuit of Si SET

5 Operation of SET Single-electron Transistor (SET) Vd is small Cs Vg + + Cg + Vd The same number of electrons Ngate = CgVg/e Nisland = Integer Cd SET island Current flows only when the number of electrons in the gate is half-integer Number of electrons in the island VgCg/e Current (Conductance) oscillates as a function of gate voltage (Vg)

6 Single-Electron Transistor Gate electrode Vg Silicon island Vd Source e - Drain Tunnel Barrier Structure of SET Difficulties in fabricating SETs Formation a small island (~10 nm) Attaching two tunnel barriers to the island

7 Strategy for Size Reduction SIMOX (Very thin Si layer) EB lithography Size Reduction Veretical Lateral Three Dimensions Theremal Oxidation

8 Pattern-Dependent Oxidation (PADOX) Self-aligned formation of a single Si island 1D-Wire Si Island (SET) SET Gate electrode DrDrain Island Source Buried SiO2 Substrate SIMOX Wire Size Width=30 nm Length= nm Height=30 nm Si layer (Y. Takahashi, IEDM 1994) Quantum size effect Potential Poisson Stress

9 Pattern-Dependent Oxidation (PADOX) Self-aligned formation of a single Si island 1D-Wire Gate electrode DrDrain Si Island (SET) Tunnel capacitor Source Gate Cg Drain Cs Cd Source Buried SiO2 Substrate SIMOX Wire Size Width=30 nm Length= nm Height=30 nm Si layer Island Cb Substrate "Single-Electron Transistor (SET)" (Y. Takahashi, IEDM 1994)

10 I-Vg Characteristics of Si SET Drain current (na) Number of electrons T = 40 K L = 70 nm, W = 40 nm, V d = 1mV Gate Voltage (V)

11 Characteristics of Si SET Fabricated by PADOX 20x10-9 Conductance (S) T = 40 K L = 70 nm, W = 40 nm, V d = 10 mv Excited states Gate Voltage (V) 4.0 large charging energy and exited states

12 Stability of I-Vg I Characteristics Drain Current (na) T = K Vd = 10 mv June 10, years April 16, Gate Voltage (V) Gate Voltage (V)

13 Threshold Voltage Threshold Voltage Voltage (V) for 1-st Electron (V) for 1-st 1 Electron V fp V fp - e/(2c fg ) Increase by quantum size effect Almost constant & -100 mv Gate Capacitance C fg (af) (af) 2.5 Island size

14 Advantages of Si SET (PADOX) Small Total Capacitance ~1 af (~300 K) Integration of Small Islands Reproducible and Controllable Fabrication Process (Capacitance and Conductance) Very Stable Operation like a MOSFET (No Effects of Offset Charge) Same Process as for Si MOS LSI/SOI

15 Logic Applications of Si SET

16 Logic Applications of Si SET Special Features of SET Oscillatory I-Vg Characteristics Operattion as a p-type and n-type Switch (CMOS-type Inverter, Adder) Multiple-valued Operation (Multiple-valued memory, Quantizer) Multigate Capavility Gate-Level Summation (X-OR gate, Multi-bit Adder)

17 CMOS-type of SET Logic

18 CMOS-type Single-Electron Inverter p-switch VDD GND Input Output n-switch GND VDD Two SETs are connected in series J. R. Tucker, JAP, 72, 4339 (1992).

19 SETs Connected Series (V-PADOX) AFM Image SET VDD Top Gate (Input) GND Control Gate A (VA) Control Gate B (VB) Y. Ono et al., APL, 76, 3121 (2000). SET Output

20 Inverter Operation VA = 0 V VB = 7 V Y. Ono et al., APL, 76, 3121 (2000). Input-Output Transfer Characteristics Output Voltage (mv) VDD = 20 mv T = 27 K T = 30 K dvout/dvin = Input Voltage (mv) Transfer of signal & CMOS-type logic

21 Multiple-Gate Si SET

22 Multi-gate MOSFET & SET Multi-gate MOSFET Multi-gate SET T. Shibata et al., IEEE Tras. ED, 39, 1444 (1992). Y. Takahashi et al., APL, 76, 637 (2000).

23 Multi-gate SET (X-OR gate) Multi-gate SET Cgi = Cg0 (I =1,2 N) V H ini = e/2cg0 Even number of High-gate Odd number of High-gate Y. Takahashi et al., APL, 76, 637 (2000). Low states High states

24 SEM Images of Dual-gate SET Dual-gate SET (Parallel Gates) Drain SET Island Drain 200 nm Gate nm Source Si wire (SET) Source Gate 2 Ultra fine parallel gate (XOR Gate) Y. Takahashi et al., APL, 76, 637 (2000).

25 XOR Operation of Dual-gate SET V in1 Cg1 Id Vdd SET Cg1= 0.42 af Cg2= 0.36 af V in2 Cg2 Y. Takahashi et al., APL, 76, 637 (2000).

26 Multiple-Valued Application of SET

27 Multiple-Valued Application Corresponding to Electron Number Multiple-valued Memory V V gg I d V gs I MOSFET SET I o V ds V gg -V th I-Vg charac. (Current Output) I d I MOSFET V gs Number of Electrons Multi-stable Voltage Output I o H. Inokawa et al., DRC, (2001). V

28 Integrated SET and MOSFET Top View Gate poly-si Silicon-On- Insulator SET MOSFET H. Inokawa et al., DRC, (2001).

29 Multiple-Valued Application Corresponding to Electron Number Multiple-valued Memory Word line Memory node I Memory node Vgg Stable Points V I o I 0 MOS FET1 SET H. Inokawa et al., DRC, (2001). MOS FET2 Bit line SET MOSFET2 MOSFET1 400 nm

30 SET-MOSFET 2-terminal 2 I-V I I (na) V (V) H. Inokawa et al., DRC, (2001). a b c d e f stability points I o

31 Single-Electron Quantizer (Multiple-Valued Operation) Pulse Generator HP8110A Function Generator HP33120A Sync V in CLK V gg I o V dd V out MOSFET V dd2 external MOSFET2 V out 2 external MOSFET1 SET R Oscilloscope HP5450C H. Inokawa et al., IEDM, (2001). V ss2 Multiple-Valued Memory

32 H. Inokawa et al., IEDM, (2001). Single-Electron Quantizer Input V in CLK f CLK : 25Hz Out put f e d c b a V out Number of Electrons in the Island

33 New Device for Single-Electron Transfer & Detection (Single-Electron CCD)

34 Single-Electron CCD Device Structure Si wire MOSFETs Stored hole n + drain #1 n + source n + drain #2 n + poly-si upper gate (sense) Buried oxide Si substrate (back gate) Hole potential Stored hole Gate oxide Si layer n + poly-si lower gate (front) Valence band Transfer of single hole A. Fujiwara et al., Nature, 410, 560 (2001).

35 Single-Electron CCD Structure & Operation principle Electric field (~10 5 V/cm) Vfg <0 Si wire Sense gate (Top gate) Hole Electrons V bg >0 Electron-hole separation (15 nm) Front gate (Fine gate) Si wire 20 nm Oxide Back gate Sense current Sensed by by electron electron current current A. Fujiwara et al., Nature, 410, 560 (2001).

36 Sensing of Single-Hole oxide back gate flow of electrons Si Gate Capacitance ~10 af (90 nm-long Si wire MOSFET) e 2 /C~ 16 mev front gate Stored holes n h Current (A) Hole generation by illumination T=25K Sense Gate Voltage n h =3 n h =4 n h =5 n h =6 0.0 nh =0 n h =1 n h = SenseGateVoltage(V) V d =0.1V V fg =-1.6V V bg =60V No illumination n h =0 1.5 A. Fujiwara et al., Nature, 410, 560 (2001).

37 Single-Hole Transfer <Sense> V sg =0.88 V (high) Current#1 Current#2 <Transfer> V fg1 V fg2 V sg =-1 V (low) V fg1 :-1.3 V -2.5 V Current #1 (A) #1 #2 < Sense (n h, n h )> < Transfer > T=25 K (0, 1) (1,0) (0,1) (1,0) Current #2 (A) Time (s) A. Fujiwara et al., Nature, 410, 560 (2001).

38 Room Temperature Operation of Single-Hole CCD 2 1 n h =5 4 3 n h =0 Hole storage by One-shot illumination

39 Summary PADOX: Pattern-Dependent Oxidation Self-aligned formation of small Si islands Small size, Reproducible & Controllable, Stable operation, Compatible with Si MOS LSI Multiple-gate structure Multiple-peak characteristics Flexible fabrication for SETs Single-electron Logic Circuit (Inverter, Adder, X-OR, Multiple-valued logic)

40 Summary New Device: Single-Electron CCD Simple structures High temperature operation Single-electron Transfer & Ditection

41 End of Presentation Yasuo Takahashi