MODULE-2: Field Effect Transistors (FET)

Transcription

1 FORMAT-1B Definition: MODULE-2: Field Effect Transistors (FET) FET is a three terminal electronic device used for variety of applications that match with BJT. In FET, an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between controlling and controlled quantities.in a Field effect device current is controlled by the action of an electron field, rather than carrier injection. The main difference between BJT and FET is BJT is a current controlled device while FET is a voltage controlled device. This is shown in fig 1. Fig 1: Comparison between BJT and FET TYPES OF FETS: 1. Junction Field Effect Transistors(JFETs) 2. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) JUNCTION FIELD EFFECT TRANSISTORS(JFETS): JFET is a unipolar device as conduction in the device is dependent on either electrons or holes. Accordingly there are two types of JFET; namely: n-channel JFET and p-channel JFET. Features of FET: FET is a voltage controlled device. FET is a unipolar device. FET has high input impedance AC voltage gain of JFET is low FET has higher temperature stability. FET are small in size and hence are useful in ICs. CONSTRUCTION AND CHARACTERISTICS OF N-CHANNEL JFET: The basic construction of the n-channel JFET is as shown in fig 2. The major part of the structure is the n-type material which forms the channel between embedded layers of p- 1

2 type material. The top of the n-type channel is connected through an ohmic contact to a terminal referred to as the drain(d), where as the lower end of the material is connected through an ohmic contact referred to as source(s). The 2 p-type materials are connected together to the gate (G) terminal. In the absence of any applied potentials, JFET has 2 p- n junctions under no bias condition. As a result, depletion region is formed at each junction. Fig 2 Construction of n- channel JFET OPERATION: Fig 3 shows the working of n-channel JFET for different gate-source voltage (V GS ) and drain to source voltage (V DS ) = 0V. Fig 3: Operation of n-channel JFET Case i: V GS = 0 and V DS = 0 2

3 Under zero bias condition depletion region around the p-n junction is thin and thus exhibits low channel resistance. Case ii: V GS = 0 and V DS = + small voltage. The gate and source are at the same potential and the instant the voltage VDS is applied the electrons in the n-channel are drawn towards the drain terminal establishing drain current (ID). Due to reverse biasing of the p-n junction for the length of the channel results in gate current = 0. As VDS is increased further, the drain current increases. When VDS = VP, the depletion region widens causing reduction in the channel width. The reduced path of conduction causes the resistance to increase and the current saturates. When VDS is further increased, the two deletion regions touch resulting in pinch-off condition. The drain characteristics (plot of ID vs VDS for VGS = constant is as shown in fig 4. Case iii: V GS = -ve voltage and V DS = + small voltage. The effect of applied reverse bias on gate and source widens the depletion regions around the p-n junctions but at the lower levels of VDS. The resulting saturation level for ID is reduced and will continue to decrease as VGS is made more and more negative. The drain characteristics is as shown in fig 5 for different values of VGS. When VGS = -VP, pinch-off condition occurs resulting in ID = 0. VP is called pinchoff voltage. The region to the left of pinch off locus is called ohmic region and the region to the right of pinch-off locus is saturation region. This region of JFET is employed for linear amplifiers. In ohmic region JFET can be employed as a variable resistor. The resistance is controlled by VGS. As VGS becomes more and more negative, the slope of the characteristics becomes more and more horizontal indicating increasing resistance level. The resistance is given by the equation 1. Fig 4 : Drain characteristics of n-channel JFET for VGS = 0V. 3

4 Fig 5 :Drain characteristics of JFET for different V GS values. TRANSFER CHARACTERISTICS OF N-CHANNEL JFET: Transfer characteristics are a plot of I D as a function of V GS with V DS as constant. Shockley Equation as in equation 1 is used to plot transfer characteristics. V I D = I DSS 1 - V Eqn (1) I D depends on V GS in a non-linear manner. As a result, FET s are often referred to square law devices. Using the drain characteristics on the right of Y-axis, we can draw a horizontal line from the saturation region of the curve denoted as V GS = 0V to the I D axis. The resulting current level for both the graphs is I DSS. When V GS =V P, the drain current is 0mA, defining another point on transfer curve. Transfer curve is a direct transfer from input to output variables. Transfer characteristics are a parabolic curve as shown in fig 6. GS P 2 4

5 Fig 6: Transfer characteristics from drain characteristics TRANSFER CHARACTERISTICS: SHORT-HAND METHOD Transfer characteristics can also be obtained by applying following conditions to schokley s equation (1). Condition1: VGS = 0 V I D = I DSS 1 - V GS P 2 Therefore I D = I DSS. Condition 2:V GS = V P Therefore from equation 1 I D = 0mA. Condition 3: V GS = V P /2 Therefore from equation 1, I D = I DSS /4 Condition 4: I D = I DSS /2 5

6 From eq(1), Points are marked for these conditions of VGS and ID and the co-ordinates are joined using smooth curve. CONSTRUCTION AND CHARACTERISTICS OF P-CHANNEL JFET: The basic construction of the p-channel JFET is as shown in fig 2. The major part of the structure is the p-type material which forms the channel between embedded layers of p- type material. The top of the p-type channel is connected through an ohmic contact to a terminal referred to as the drain(d), where as the lower end of the material is connected through an ohmic contact referred to as source(s). The 2 n-type materials are connected together to the gate (G) terminal. In the absence of any applied potentials, JFET has 2 p- n junctions under no bias condition. As a result, depletion region is formed at each junction. Fig 7 Construction of n- channel JFET OPERATION OF P-CHANNEL JFET: Case i: V GS = 0 and V DS = 0 6

7 Under zero bias condition depletion region around the p-n junction is thin and thus exhibits low channel resistance. Case ii: V GS = 0 and V DS = -ve small voltage. The gate and source are at the same potential and the instant the voltage VDS is applied the holes in the p-channel are drawn towards the drain terminal establishing drain current (ID). Due to reverse biasing of the p-n junction for the length of the channel results in gate current = 0. As VDS is increased further, the drain current increases. When VDS = -VP, the depletion region widens causing reduction in the channel width. The reduced path of conduction causes the resistance to increase and the current saturates. When VDS is further increased, the two deletion regions touch resulting in pinch-off condition. The drain characteristics (plot of ID vs VDS for VGS = constant is as shown in fig 8). Case iii: V GS = +ve voltage and V DS = -ve small voltage. The effect of applied reverse bias on gate and source widens the depletion regions around the p-n junctions but at the lower levels of VDS. The resulting saturation level for ID is reduced and will continue to decrease as VGS is made more and more positive. The drain characteristics are as shown in fig 8 for different values of VGS. When VGS = -VP, pinch-off condition occurs resulting in ID = 0. VP is called pinchoff voltage. Fig 8: Drain Characteristics of p-channel JFET Symbols of JFET: Fig 9(a) and 9 (b) shows the symbols of n-channel and p- channel FET respectively. 7

8 Drai Drai Gate Gate Fig 9: JFET Symbols. 9(a) n-channel JFET Source Source 9(b)p-channel JFET Metal Oxide Semiconductor Field Effect Transistors (MOSFETs): MOSFET is a type of Field Effect Transistor in which majority charge carriers flow in the channel. The width of the channel is controlled by an electrode called gate. Channel width determines how well the device conducts. MOSFETS are useful in high-speed switching circuits and in Integrated Circuits. There are two types of MOSFET s: (i) (ii) Depletion type MOSFET Enhancement type MOSFET DEPLETION TYPE MOSFET: Depletion-type MOSFETs are further classified as (i) N-channel D-type MOSFET (ii) P-Channel D-type MOSFET N-CHANNEL DEPLETION TYPE MOSFET: The basic construction of the n-channel depletion type MOSFET is as shown in fig (10). A slab of p-type material is formed from a Si base and is referred to as the substrate. The source and drain terminals are connected through metallic contacts to n-doped regions linked by a n-channel. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin SiO 2 layer. The presence of SiO 2 layer accounts for very high input impedance of the device. The input impedance of MOSFET is higher than JFET. 8

9 Fig 10: Construction n-channel Depletion type MOSFET. A small n layer is implanted in the region below SiO 2 to create n-channel. The insulating layer between gate and the channel has resulted in another name for the device : Insulated-gate FET or IGFET. OPERATION OF N-CHANNEL DEPLETION MODE MOSFET: Case i: V GS = 0 and V DS = +ve voltage Since drain is positive with respect to source, the free electrons are attracted from source to drain to constitute drain current I D. The drain characteristics and transfer characteristics of depletion mode MOSFET is as shown in fig 11. Case ii: V GS = -ve Voltage and V DS = +ve small voltage The negative potential at the gate will cause the electrons to move towards p-type substrate as charges repel while holes from p-type substrate are attracted toward gate. Depending on the magnitude of negative bias established by V GS, a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction. The more negative the bias, higher is the rate of recombination. The resulting level of I D is reduced with the increasing levels og negative bias for VGS as in fig11. 9

10 Fig11(a) Transfer Characteristics Fig 11(b) Drain Characteristics. Case iii: V GS = +ve Voltage and V DS = +ve small voltage For positive values of V GS, the +ve gate will draw additional electrons from p-type substrate as minority charge carriers are attracted towards gate. New carriers are generated due to collisions and I D will increase at a rapid rate. Thus, application of +V GS has enhanced the level of free carriers in the channel compared to V GS = 0V. The region of +ve gate voltage on the drain or transfer characteristics is referred as enhancement region. The region between the cut-off and the saturation level of I DSS is refereed as the depletion region. Transfer characteristics are a plot of I D as a function of V GS with V DS as constant. Shockley Equation as in equation 2 is used to plot transfer characteristics Eqn (2) V I D = I DSS 1 - V GS P 2 Also, Short hand method can be used to plot transfer characteristics curve. Condition1: V GS = 0, Hence from eq(2), 10

11 I D = I DSS. Condition 2:V GS = V P Therefore from equation 2 I D = 0mA. Condition 3: V GS = V P /2 Therefore from equation 2, I D = I DSS /4 Condition 4: I D = I DSS /2 From eq(1), Points are marked for these conditions of VGS and ID and the co-ordinates are joined using smooth curve. P-CHANNEL DEPLETION TYPE MOSFET: The basic construction of the p-channel depletion type MOSFET is as shown in fig (12a). A slab of n-type material is formed from a Si base and is referred to as the substrate. The source and drain terminals are connected through metallic contacts to p-doped regions linked by a p-channel. The gate is also connected to a metal contact surface but remains insulated from the p-channel by a very thin SiO 2 layer. The presence of SiO 2 layer accounts for very high input impedance of the device. The input impedance of MOSFET is higher than JFET. 11

12 Fig 12: (a) Construction (b) Transfer Characteristics (c) Drain characteristics OPERATION OF P-CHANNEL DEPLETION MODE MOSFET: Case i: V GS = 0 and V DS = -ve voltage Since drain isnegative with respect to source, the holes are attracted from source to drain to constitute drain current I D. The drain characteristics and transfer characteristics of depletion mode MOSFET is as shown in fig 12(c) and (b) respectively. Case ii: V GS = +ve Voltage and V DS = -ve small voltage The positive potential at the gate will cause the holes to move towards n-type substrate as charges repel while electrons from n-type substrate are attracted toward gate. Depending on the magnitude of positive bias established by V GS, a level of recombination between electrons and holes will occur that will reduce the number of holes in the p-channel available for conduction. The more positive the bias, higher is the rate of recombination. The resulting level of I D is reduced with the increasing levels or positive bias for V GS as in fig12(c). Case iii: V GS = -ve Voltage and V DS = -ve small voltage For positive values of V GS, the -ve gate will draw additional holes from n-type substrate as minority charge carriers are attracted towards gate. New carriers are generated due to 12

13 collisions and I D will increase at a rapid rate. Thus, application of -V GS has enhanced the level of free carriers in the channel compared to V GS = 0V. Transfer characteristics are a plot of I D as a function of V GS with V DS as constant. Shockley Equation as in equation 2 is used to plot transfer characteristics Eqn (3) V I D = I DSS 1 - V GS P 2 Also, Short hand method can be used to plot transfer characteristics curve. Condition1: V GS = 0, Hence from eq(3), I D = I DSS. Condition 2:V GS = V P Therefore from equation 2 I D = 0mA. Condition 3: V GS = V P /2 Therefore from equation 2, I D = I DSS /4 Condition 4: I D = I DSS /2 From eq(1), Points are marked for these conditions of V GS and I D and the co-ordinates are joined using smooth curve. SYMBOLS OF DEPLETION TYPE MOSFET Fig 13 shows the symbols of n-channel and p-channel Depletion mode MOSFET. 13

14 Fig 13 (a) n-channel depletion type MOSFET (b) p-channel depletion type MOSFET N-CHANNEL ENHANCEMENT-MODE MOSFET (E-MOSFET): The construction of n-channel enhancement mode MOSFET is as shown in fig 14. The starting material is a p-type substrate into which highly doped n-regions are diffused to form source and drain regions. A layer of SiO 2 is grown allover the p-type substrate and is etched to create window for n-diffusion. The source and drain terminals are taken out through metallic contacts to n-doped regions as shown in fig 14. Metal is deposited on SiO2 to create Gate. The presence of SiO2 between gate and p-substrate provides electrical isolation between the two regions. No channel exists between source and drain in E-MOSFET. Fig 14: Construction of n-channel E-MOSFET OPERATION OF N-CHANNEL E-MOSFET: Case i: V GS = 0 and V DS = +ve voltage 14

15 The application of drain to source voltage while gate and source are shorted will cause no ID to flow as no channel exists for this condition. Case ii: V GS = +ve Voltage and V DS = +ve small voltage When gate is made positive with respect to source, electrons are attracted towards the gate but holes are repelled back into p-type substrate. Since the region under the gate is p- type substrate, the positive voltage on gate causes holes which are majority charge carriers in p-type substrate to repel and move towards substrate. A positive V GS and positive V DS causes the two pn junctions to be reverse biased and depletion region is formed. Now the device is said to be in depletion mode. The positive V GS also causes electrons to be attracted towards the gate. Now, device is said to be in accumulation mode. Since the region below the gate was p-substrate and accumulation of electrons has caused the type to change to n-type. Thus the device is said to be in inversion mode as shown in fig 15. A positive V GS has caused a thin layer of negative chargesto be formed in the substrate under the gate. Thus, channel is said to be created. The value of V GS which causes channel to be formed under the gate is called threshold voltage(v T ). A small I D flows. When V GS is increased above V T, conductivity of the channel is enhanced and thus pulling more electrons into the channel. When V GS <V T, there is no channel. Since channel is formed by the application of +V GS, the type of MOSFET is Enhancement type. As V GS is increased further, higher level of I D flows as shown in fig 16. A positive V GS cause potential drop across the channel. For large V DS this voltage may not be sufficient to invert the channel near the drain end there by causing drain current to saturate. The channel is said to be pinched off. I D flows due to diffusion. Fig 15: Formation of Inversion layer TRANSFER CHARACTERISTICS OF N-CHANNELE-MOSFET: The transfer characteristics of n-channel E-MOSFET is as shown in fig 16. For VGS >VT, the relationship between drain current and VGS is nonlinear and is given by eqn Eq 4 Where K is a constant and is a function of the construction of the device as given by Eqn Eq 5 15

16 Fig16: Transfer Characteristics Drain Characteristics Thus I D increases steadily when V GS > V T and I D is zero when V GS < V T. p-channelenhancement-mode MOSFET (E-MOSFET): The construction of p-channel E-MOSFET is opposite to that of n-channel E_MOSFET. Substrate is of n-type and source, drain are of p-type as in fig17(a). The voltage polarities and current directions are reversed in p-channel E-MOSFET. The drain and transfer characteristics of p-channel E-MOSFET are as shown in Fig 17 (c) and (b) respectively. Fig 17: (a) Construction (b) Transfer Characteristics (c) Drain Characteristics OPERATION OF P-CHANNEL E-MOSFET: 16

17 Case i: V GS = 0 and V DS = -ve voltage The application of drain to source voltage while gate and source are shorted will cause no ID to flow as no channel exists for this condition. Case ii: V GS = -ve Voltage and V DS = -ve small voltage When gate is made negative with respect to source, holes are attracted towards the gate but electrons are repelled back into n-type substrate. Since the region under the gate is n- type substrate, the negative voltage on gate causes electrons which are majority charge carriers in n-type substrate to repel and move towards substrate. A negative V GS and negative V DS causes the two pn junctions to be reverse biased and depletion region is formed. Now the device is said to be in depletion mode. The negative V GS also causes holes to be attracted towards the gate. Now, device is said to be in accumulation mode. Since the region below the gate was n-substrate and accumulation of holes has caused the type to change to p-type. Thus the device is said to be in inversion mode.a negative V GS has caused a thin layer of positive charges to be formed in the substrate under the gate. Thus, channel is said to be created. The value of V GS which causes channel to be formed under the gate is called threshold voltage(v T ). A small I D flows. When V GS is decreasedbelow V T, conductivity of the channel is enhanced and thus pulling more electrons into the channel. When V GS >V T, there is no channel. Since channel is formed by the application of -V GS, the type of MOSFET is Enhancement type. The drain characteristics are as shown in fig 17 (c). TRANSFER CHARACTERISTICS OF P-CHANNEL E-MOSFET: The V GS is negative and I D flows in opposite direction. The transfer characteristics of p- channel E-MOSFET is as shown in fig 17(b). I D increases steadily with V GS. E-MOSFET SYMBOLS: Fig 18 (a) and 18(b) shows the symbols of n-channel and p-channel E-MOSFET. Fig 18: E-MOSFET Symbols FET CONFIGURATION: 17

18 The three types of FET configuration are: (i) Common Source (CS) Configuration (ii) Common Drain (CD) Configuration (iii)common Gate (CG) Configuration FET BIASING: Biasing is done to establish proper levels of DC voltages and currents for desired region of operation. It establishes Q-point. TYPES OF BIASING: (i) Fixed Bias (ii) Self Bias (iii)voltage divider Bias Voltage divider bias most widely used biasing technique in amplifiers. FET AS AN AMPLIFIER: Fig.19 Shows Common Source Circuit. The Voltage V GG provides the necessary reverse-bias between gate and source of JFET. The signal to be amplified is V S. The transfer Characteristics of JFET is as shown in Fig. 20. A DC load line is drawn on the characteristics. The point of intersection of DC load line on Transfer characteristics for specific V GS is called Q point. Let Q point be situated at the middle of DC load line. Fig 19: CS Amplifier with Fixed Bias Fig 20: Locate Q-Point The instantaneous V gs is V gs =V S -V GG (6) Both I D and V DS can be considered as sinusoid superimposed on the DC values. 18

19 Then V GS =-V GG +V gs (7) I D =i d +I DQ V OUT =V DS =V DSQ +V ds (8) Since output signal is greater than input signal, amplification has occurred. The magnitude of Voltage gain is the ratio of output voltage to input voltage. A V = The selection of Q point at the middle gives undistorted output. If the operating point is located either closer to ohmic region or near pinch-off voltage, the output waveform will be clipped during +Ve or Ve half cycles. In Common Source circuit, output is out of phase with input. To locate Q point, the following procedure is used Plot transfer characteristics Draw a vertical line(load line) from VGS = -VGG. Intersection of load line with transfer characteristics will give Q point. Fig 20 shows the position of Q point using the above procedure. JFET parameters Transconductance: The change in the Drain Current due to change in Gate to Source voltage is defined as Transconductance g m. g m = We know that, I D = I DSS ( ) (9) And g m = Differentiate Eq. (9) w.r.t V GS = I DSS 2 ( ) ( ) g m = ( ) (10) Also from Eq. (9) = (11) Therefore substitute Eq. (11) in Eq. (10), we get, g m = = therefore g m = (12) when V GS =0, g m = g mo therefore from Eq. (10), g mo = (13) Substitute Eq. (13) in Eq. (10) we get, g m = g mo ( ) 19

20 Drain Resistance, r d : The ratio of change in Drain to Source voltage to change in Drain current is called Drain resistance, r d with constant V GS. r d = V GS=constant r d determines the output impedance Z O of the JFET amplifier. JFET small signal model: Fig. (21) shows low frequency small signal model for n-channel JFET. The relationship between I D and V GS is = g m V gs and hence a current Source is connected from Drain to Source. The input impedance of JFET is high and hence I G =0. Thus in the small signal model input impedance is representated by open circuit. The output impedance is representated by r d from Drain to Source. Fig. (21) n-jfet small signal model Approximate model Since r d >> external Drain resistance R D, r d can be replaced by open circuit as shown in Fig. (22). Fig. (22) Approximate small signal model of n-jfet. 20

21 COMMON SOURCE (CS) AMPLIFIER WITH FIXED BIASING: Fig 23: CS Amplifier with Fixed BiasFig 24: DC equivalent Circuit Fig 23 shows CS amplifier with fixed bias.rg is used to limit current in case VGG is connected with wrong polarity This would forward bias the gate-source junction causing high currents, which would destroy the transistor DC Analysis: Open circuit C 1 & C 2 and current through RG i.e. IG=0. Therefore RG is represented by short circuits as shown in Fig. (24) Apply KVL to the input circuit of Fig. (24) V GG -V GS =0 V GS =-V GG (14) Since V GG is constant, V GS is fixed and hence the name fixed bias. Apply KVL to output circuit V DD -I D R D -V DS =0 V DSQ =V DD -I D R D (15) And I D for fixed bias is I DQ = I DSS ( ) 2 Therefore Q point is [ ] Small signal analysis: (i) To obtain AC equivalent circuit, short circuit C 1, C 2 and reduce DC voltages to zero. 21

22 (ii) Replace JFET by its small signal model to obtain AC equivalent circuit Fig. (25). Fig 25: ac equivalent circuit Z i : From the circuit, Fig. (25) Z i =R G Zo: Reduce V i =0, V gs =0 therefore g m V gs =0. Z o =R D ǁr d Ifr d >> R D, Then Z o =R D Voltage gain, A V: A V = = From Fig. (25) V o = - g m V gs (r d ǁR D ) and V i =V gs A V = - g m V gs (r d ǁR D ) If r d >> R D, A V = - g m R D The negative sign indicates there is a phase shift of voltages. between input and output COMMON SOURCE (CS) AMPLIFIER WITH SELF BIAS: Fig 26 shows Common Source amplifier with self bias. Voltage across RS determines gate to source voltage. Dc equivalent circuit is obtained by open circuiting all capacitors as shown in fig 27. Apply KVL to Fig27, -V GS -V S =0 V S = -V GS. Also, V S = I D R S Therefore, V GS = -I D R S Apply KVL to output circuit of fig27, V DS = V DD I D R S -I D R D 22

23 Fig 26. CS amplifier with Self Bias Fig 27 DC equivalent Circuit Fig 28 : Q point Fig 8 shows the location of Q point obtained by following procedure. Plot transfer characteristics Plot one point of load line at V GS =0, I D = 0. Second point can be obtained by choosing I D and finding V GS. I D =I DSS /2, then V GS = -I D R S = -I DSS R S /2 Join two points to draw DC load line Intersection of load line with transfer characteristics will give Q point. CS amplifier with Self Bias(Bypassed Rs) ac analysis 23

24 Fig 29 shows CS amplifier with Self bias and RS is bypassed by CS. Fig 30 shows ac equivalent Circuit obtained by short circuiting C1,C2,CS. Fig 29: CS amplifier with Self Bias Fig 30: ac Equivalent Circuit. Replacing JFET by its equivalent small signal model results in circuit shown in Fig 31. Fig 31: AC equivalent model of CS amplifier with Self bias Z i : From the circuit, Fig. (31) Z i =R G Zo: Reduce V i =0, V gs =0 therefore g m V gs =0. Z o =R D ǁr d Ifr d >> R D, Then Z o =R D Voltage gain, A V: A V = = From Fig. (31) V o = - g m V gs (r d ǁR D ) and V i =V gs A V = - g m V gs (r d ǁR D ) If r d >> R D, A V = - g m R D The negative sign indicates there is a phase shift of voltages. between input and output 24

25 CS amplifier with Self Bias(UnBypassedRs) ac analysis Fig 32 shows CS amplifier with self bias but RS is unbypassed. To obtain ac equivalent circuit, c1 and c2 are short circuited as shown in Fig33. Replacing JFET by its equivalent small signal model, we get the circuit shown in fig 34. Fig 32: CS amplifier with self bias Fig 33: ac Equivalent Circuit Fig 34: ac Equivalent model Zi: From Fig 34, Z i = R G. 25

26 Zo : Output impedance excluding RD. Z o = V o /I d Apply KVL to the output circuit of Fig 34, V o = I 1 r d + I d R S But, I 1 = I d -g m V gs. Therefore, V o = (I d -g m V gs ) + I d R S (16) Apply KVL to the input circuit of Fig 34, V i -V gs -I d R S = 0 V gs = -I d R S + V i For output impedance, V i = 0. Therefeore, V gs = -I d R S (17) Substituting Eq (17) in (16) V 0 = I d (r d +g m R S r d +R S ) Therefore, Z o = V o /I d = r d + g m R S r d + R S But, µ = g m r d Therefore, Z o = r d + R S (µ+1) (18) Thus, output impedance with unbypassed RS is increased. Zo: Output impedance considering RD Zo = Z 0 R D Voltage Gain,AV: From Fig 34, V o = -I d R D (19) Apply KVL to the outer part of Fig 34, (I d -g m V gs )r d + I d R D + I d R S = 0; (20) Also V gs = V i I d R S (21) Eq (21) in Eq (20) I d = (g m V i r d )/(r d + g m R S r d + R s + R D ) (22) Eq (22) in Eq (19) V o = (-g m V i r d R D )/(r d + g m R S r d + R S + R D ) A V = V o /V i = -g m r d R D /r d + g m R S r d + R S + R D If r d >> R S +R D, A V = -g m R D /(1+g m R S ) Example: For the CS amplifier shown, operating point is defined by V GSQ = -2.5V, V P = - 6V and I DQ = 2.5mA with I DSS = 8mA.Calculate g m, r d,z i,z o and A V. Take Yos = 20µS (i) g m = g mo ( ) 26

27 g mo = = = 2.67mS g m = g mo ( ) = ( ) = 1.58mS (ii) r d = = = 50KΩ (iii) Z i = R G = 1MΩ (iv) Zo = Z 0 R D = r d + R S (µ+) RD = Ω (v) A V = = -g m r d R D /r d + g m R S r d + R S + R D = CS amplifier with Voltage Divider Bias(Bypassed Rs): Fig 35 Shows voltage divider bias circuit. Fig 35: Voltage Divider Bias DC analysis: Open circuit C1, C2, CS and the resultant circuit is as shown in Fig

28 Fig 36: DC Equivalent Circuit. From Fig 36, V G = V DD R 2 R + R 1 2 -V G + V GS + IDR S = 0 V = V - I R GS G D S V DS = V DD - I D (R D + R S) Fig 37 shows the procedure to fix Q point in voltage divider bias. Fig 37: Fixing Q Point. 28

29 AC Analysis: AC Equivalent Circuit is obtained by Shorting C1, C2 and CS as shown in Fig 38. Replacing JFET by its small signal model, we get the circuit shown in Fig 39. Fig 38: AC Equivalent Circuit Fig 39: AC Equivalent model Z i : From the circuit, Fig. (39) Z i =R 1 R 2 Zo: Reduce V i =0, V gs =0 therefore g m V gs =0. Z o =R D ǁr d Ifr d >> R D, Then Z o =R D Voltage gain, A V: A V = = From Fig. (39) V o = - g m V gs (r d ǁR D ) and V i =V gs A V = - g m V gs (r d ǁR D ) If r d >> R D, A V = - g m R D The negative sign indicates there is a phase shift of voltages. between input and output CS amplifier with Voltage Divider Bias (UnBypassed Rs): ac Analysis Fig 40 Shows CS voltage divider bias with un-bypassed RS. AC Analysis is obtained by short circuiting C1,C2 and the resultant circuit is shown in Fig 41. Replacing JFET by its equivalent small signal model, we get circuit shown in Fig

30 Fig 40: CS amplifier with Voltage Diver Bias Fig 41: Ac Equivalent Circuit Fig 42: AC equivalent Model Zi: From Fig 42, Z i = R 1 R 2. Zo : Output impedance excluding RD. Z o = V o /I d Apply KVL to the output circuit of Fig 42, V o = I 1 r d + I d R S But, I 1 = I d -g m V gs. Therefore, V o = (I d -g m V gs ) + I d R S (23) Apply KVL to the input circuit of Fig 42, V i -V gs -I d R S = 0 30

31 V gs = -I d R S + V i For output impedance, V i = 0. Therefeore, V gs = -I d R S (24) Substituting Eq (24) in (23) V 0 = I d (r d +g m R S r d +R S ) Therefore, Z o = V o /I d = r d + g m R S r d + R S But, µ = g m r d Therefore, Z o = r d + R S (µ+1) (25) Thus, output impedance with unbypassed RS is increased. Zo: Output impedance considering RD Zo = Z 0 R D Voltage Gain,AV: From Fig 42, V o = -I d R D (26) Apply KVL to the outer part of Fig 42, (I d -g m V gs )r d + I d R D + I d R S = 0; (27) Also V gs = V i I d R S (28) Eq (27) in Eq (26) I d = (g m V i r d )/(r d + g m R S r d + R s + R D ) (29) Eq (22) in Eq (19) V o = (-g m V i r d R D )/(r d + g m R S r d + R S + R D ) A V = V o /V i = -g m r d R D /r d + g m R S r d + R S + R D If r d >> R S +R D, A V = -g m R D /(1+g m R S ) Common Drain (CD)/ Source Follower Configuration: Fig. (43) shows Common Drain configuration. The input is applied between Gate and Source and output between Source and Ground (i.e. Drain is grounded during AC analysis) Fig 43: Source Follower Circuit From the circuit in Fig 43, V G + V GS V S = 0 Therefore V G + V GS = V S When a signal is applied to JFET gate via C 1, V G varies with the signal. As V GS is constant and V S = V G + V GS varies with V i. As the output voltage at the Source (V S ) 31

32 follows changes in the signal voltage applied to the gate, this circuit is also called Source follower. The AC equivalent circuit and low frequency equivalent model for Source follower is as shown in Fig. (44) and Fig. (45) respectively. Fig. (44) AC Equivalent Circuit Fig. (45) AC Equivalent Model V i -V gs -V o =0 V o =V i -V gs V o + V gs -V i =0 V gs =V i -V o V i =0, V gs =-V o Z i : From the input circuit, Z i = R G Output Z:Z o Fig. (45) can also be written as Fig. (46) = Apply KVL to the output loop of Fig 46, V i -V gs -V o =0 For Z o, V i =0, V o =V gs But from Fig. (46), I d =g m V gs Fig (46) AC Equivalent Model 32

33 Therefore g m V o = I d = = Therefore Z o ǁ R S Z o = ǁ R S Voltage Gain, A V A V = From Fig. (46), V o = I d (r d ǁ R S ) And I d = g m V gs Therefore V o = g m V gs (r d ǁ R S ) From input circuit V i = -V gs +V o Therefore V i = - g m V gs (r d ǁ R S ) - V gs Therefore A V = = A V = If A V = [ ] ; r d R S R S [ ] If >> 1, A V 1 but it is always less than one. There is no phase shift between input and output voltages. Source Follower exhibits following Characteristics; High input Impedance. Low Output Impedance Voltage gain is less than 1. No phase shift between input and output. Example: A DC analysis of Source Follower network shown in Fig. below results in V GSQ = -2.86V and I DQ =4.56mA. Determine (i) (ii) r d (iii) Z i (iv) Z o with and without r d (v) A V with and without r d. Take I DSS =16mA, V P =-4V, Y OS =25μS. 33

34 (i) g mo = = = 8mS g m = g mo ( ) = ( ) g m = S. (ii) r d = = = 40KΩ (iii) (iv) (v) Z i = R G = 1MΩ With r d Z o =r d ǁ R S ǁ = 40K ǁ 2.2K ǁ = Ω Without r d Z o =R S ǁ = ǁ = Ω A V With r d A V = = [ ] A V Without r d A V = = = Common Gate (CG) Configuration: Fig. (47) shows CG configuration, the input is applied between Source and Gate and output is taken between Drain and Gate. Fig. (47) Common Gate Configuration In CG configuration, Gate voltage is constant. An increase in in positive direction increases the Ve Gate to Source bias voltages. Due to this Drain current reduces, reducing the drop I D R D. Since V D = V DD - I D R D, the reduction in I D results in an 34

35 increase in output V g V D. Similarly when input V g reduces, opposite action takes place which reduces the output voltage. Thus there is no phase shift between input and output in a Common Gate amplifier. AC equivalent model of CG amplifier is as shown in Fig. (48). Fig. (48) AC Equivalent Model = Current through r d (Fig 49) I rd =I + Therefore I = I rd (30) From the circuit, I rd = (31) Substitute Eq. (31) in Eq. (30) I = (32) But V i = - (from Fig. (49) ) Therefore I= + I= - + Fig (49) AC Equivalent Model Redrawn I * + = * + = = = Z i = ǁ R S = R S ǁ If r d R D and >> 1, Z i = R S ǁ = R S ǁ Input impedance of CG amplifier is less than CS and CD amplifier. Z o : when V i =0 i.e. when input is short circuited, the equivalent circuit is Z o =r d R D If r d R D, Z O R D A V = 35

36 V O =-I D R D and V i =-V gs Apply KVL to Fig. (b) outer loop V i + (I d -g m V gs )r d + I D R D =0 But V gs =- V i Therefore Vi + I d R d +g m V i r d + I D R D =0 Vi [1+g m r d ] + I d [r d +R D ] =0 -I d [r d +R D ] = Vi [1+g m r d ] V i = A V = = If r d R D, >>1 A V = = R D Thus there is no phase shift between input and output in CG amplifier. Example: For the network shown,if V GSQ = -2.2V and I DQ = 2.03mA. Determine g m,r d. Calculate Z i with and without r d, Z o with and without r d. Determine v o with and without r d. (i) g mo = = = 5mS g m = g mo ( ) = ( ) g m = S. (ii) r d = = = 20KΩ (iii) = = 0.31KΩ (iv) Z i = ǁ R S = R S ǁ = 0.35KΩ (v) (vi) Z O R D = 3.6KΩ Z o =r d R D = 3.05KΩ 36

37 (vii) A V = R D = 8.1 (viii) A V = = =7.02 (ix) 37