SIMULATION OF EDGE TRIGGERED D FLIP FLOP USING SINGLE ELECTRON TRANSISTOR(SET)

Transcription

1 SIMULATION OF EDGE TRIGGERED D FLIP FLOP USING SINGLE ELECTRON TRANSISTOR(SET) Prashanth K V, Monish A G, Pavanjoshi, Madhan Kumar, KavyaS(Assistant professor) Department of Electronics and Communication Engineering Dr.Ambedkar Institute of Technology Bengaluru ABSTRACT: Single-electron transistors (SET's) are often studied as elements of nanometre scale electronic circuits because they can be made very small and they can detect the motion of individual electrons. SET's have low voltage gain, high output impedances, and are sensitive to random background charges. This makes it unlikely that SET s would ever replace field-effect transistors (FET's) in applications where large voltage gain or low output impedance is necessary. The most promising applications for SET's are charge-sensing applications such as the readout of few electron memories, the readout of charge-coupled devices, and precision charge measurements in metrology. For SET technology a software SIMON (Simulation OfNanostructures) is being used to simulate the logic circuits. 1. INTRODUCTION During the last decades the feature size of MOS based circuits has dramatically decreased. Since the seventies the microelectronics industry has followed Moore s law, doubling the processing power every 18 months. The ever decreasing feature size, and the corresponding increase in the number of transistors per mm, facilitated vast improvements in semiconductorbased designs. At the same time, however, there have been reports that the transistor itself cannot be shrunk beyond certain limits dictated by its operating Principle. In order to ensure further feature size reduction, possible successor technologies with greater scaling potential such as Single Electron Tunnelling (SET) are currently under investigation. Recent advances in deep-submicron CMOS technologies have made it possible to load a small Si chip with an enormous number of transistors. However, the power consumption of the chip monotonically increases as the number of transistors increases. This will limit the integration scale because the power consumption will exceed the cooling limit. The singleelectron transistor (SET) is expected to be a key device for future extremely large-scale integrated circuits because of its ultralow power consumption and small size. The SET has a great potential for low-power yet high-performance signal processing and hence for furthering the multimedia society. Single-electron transistor (SET) is a key element of current research area of nanotechnology which can offer low power consumption and high operating speed. Single electron transistor [SET] is a new nanoscale switching device because single-electron transistor retains its Page 201

2 scalability even on an atomic scale and besides this; it can control the motion of a single electron. The single electron transistor is a new type of switching device that uses controlled electron tunnelling to amplify current. Single-electron transistors (SETs) hold great promise for future Nano electronic circuits due to their small size, low power consumption, and ability to perform fast and sensitive charge measurements SET technology is fundamentally different from CMOS as it is based on tunnelling ofelectrons. The single electron transistor is made of an island connected through two tunnelling junctions to a drain and a source electrode, and through a capacitor to a gate electrode When there is no bias on any electrode, electrons in the system do not have enough energy to tunnel through the junctions. In a SET electrons are confined within a small volume and communicate with electrical leads by tunnelling phenomenon. The tunnel junction is created by separating two conductors with a thin insulator as shown in figure 1 and therefore it behaves in principle like a capacitor. However, given that the insulator is thin enough quantum tunnelling may occur. For an electron to tunnel through the junction, the Coulomb energy, where C is the capacitance of the tunnel junction and qe is the charge of an electron, is at least needed. If the Coulomb energy is not available a tunnel event cannot happen. This phenomenon is known as Coulomb blockade. A voltage source can provide the energy needed for an electron to tunnel. Figure 1 In classical theories an electron was assumed to be well localized. However, in the quantum mechanics theory electrons are described by wave functions, indicating the probability of the presence of an electron. If a tunnel barrier is insufficiently opaque the electron wave function extends through the barrier and the electron is not clearly localized on either site of the tunnel junction. The opaqueness of a tunnel barrier is described by the tunnel resistance Rt. A sufficient condition for observing SET charging effects, where his Planck's constant. The second condition is that the charging energy Ec of single excess electron on a quantum dot is much greater than thermal energy described by The schematic structure and equivalent circuit of SingleElectron Transistor is shown in figure 2. Page 202

3 2. OPERATION OF SET Figure 2 The operation principle of a SET is shown in figure 3. A SET is adevice whose operation relies on a single electron tunneling throgh a nanoscale junction. A SET can be considered as field affect transistor (FET) whose channel consists of two tunneling junctions forming aquantum dot island. The quantum dot island is channeled to the sourse and drain, so current can flow under the influence of source bias voltage, Vs and drain bias voltage Vd respectively. The island is capacitive coupled to gate voltage, Vg. Beside that, the charging energy of the system depends on no of electrons, n on the quantum dot island and the gate voltage, Vg. Figure 3 The electrons tunnel one by one through the channel in contrast with conventional MOSFET where many electrons participate to form the drain current. 3. IMPLEMENTATION 3.1 Single Electron Box One of the conceptually simplest SET circuits in which the charge transport of a single electron can be controlled is the electron box. The electron box consists of a tunnel junction in series with Page 203

4 a capacitor, as displayed in figure 4. The tunnel junction has a capacitance of Cj and the capacitor has a capacitance of Cc Figure Transistor The SET transistor consists of two tunnel junctions in series with a capacitor attached interlaying circuit node as shown in figure 5. The resulting 3 terminal structure is similar to a MOS transistor, such that the gatevoltage Vg can control the transport of charge through the tunnel junctions. But, unlike the MOS transistor, the current Id through the SET transistor has periodic response to the input voltage Vo 3.3 Inverter Figure 5 The combination of two complementary biased SET transistors in a single circuit results in the SET inverter structure depicted in figure 6. Page 204

5 Figure 6 The SET inverter operates as follows. The upper SET transistor behaves similar to a PMOS transistor, while the lower transistor behaves similar to an NMOS transistor. Output switching (from 0 to 1 ) is accomplished by transporting electrons (typically over 100) from the output node n2 to the top supply voltage terminal Vs, or (from 1 to 0 ) by transporting electrons from the bottom ground terminal to the output node n2. 4. POSITIVE EDGE TRIGGERRED D FLIP FLOP The operations of a D flip-flop is much more simpler. It has only one input addition to the clock. It is very useful when a single data bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarize the operations of the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge Page 205

6 4.1 Output Waveforms Data input Clock Input Output Waveform Page 206

7 5. CONCLUSION This work presents the design and simulation of edge triggered D flip flop using single electron transistor. It is one of the best way to design because power consumption is less. SET is one of the developing technologies in present days. REFERENCES [1] An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology by C. MEENDERINCK, S. COTOFAN Computer Engineering Lab, Delft University of Technology Delft, The Netherlands in ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY,Volume 10, Number 1, 2007, [2] Casper Lageweg,SorinCotofana, Stamatis Vassiliadis, Single Electron Encoded Logic Circuits, Electrical Engineering Department, Delft University of Technology, Delft, The Netherlands [3] PhD Thesis of Caspar Robert LAGEWEG, Single Electron Tunneling Based Arithmetic Computation [4] Christoph Wasshuber, Hans Kosina, Member, IEEE, and Siegfried Selberherr, Fellow, IEEE, SIMON A Simulator for Single-Electron Tunnel Devices and Circuits, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 9, SEPTEMBER 1997 [5] Casper Lageweg, SorinCotofana and Stamatis Vassiliadis A Linear Threshold Gate Implementation in Single Electron Technology, Electrical Engineering Department, Delft University of Technology, Delft, The Netherlands. [6] Om Kumar and Manjit Kaur, SINGLE ELECTRON TRANSISTOR: APPLICATIONS & PROBLEMS, International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.4, December [7] Anil Kumar anddharmender Dubey Single Electron Transistor: Applications and Limitations ISSN , Volume 3, Number 1 (2013), pp Research India Publications [8] R. H. Chen, A. N. Korotkov, K. K. Likharev, "A New Logic Family Based on Single- Electron Transistors", Proc. Device Research Conference, pp , [9] Y. Yu et al., "Implementation of Single Electron Circuit Simulation by SPICE: KOSECSPICE", Proc. Asia Pacific Workshop on Fundamental and Application of Advanced Semiconductor Device, pp , Page 207

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