CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC

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1 94 CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC 6.1 INTRODUCTION The semiconductor digital circuits began with the Resistor Diode Logic (RDL) which was smaller in size, faster and with less power dissipation but compromised to some extent the I/O isolation. They were replaced by the Resistor Transistor Logic (RTL) which had a good I/O isolation but which consumed a lot of semiconductor area when fabricated on a single chip due to the large resistances. This paved the way to the Transistor-Transistor Logic (TTL) based on the bipolar transistor and the Complementary-Metal-Oxide- Semiconductor (CMOS). CMOS has a pair of complementary MOSFETs of N-type and P-type. The Bipolar-Junction Transistor (BJT) and its logic families have been replaced in a lot of applications by the CMOS due to its lower power dissipation and small area. As the CMOS is scaled down to smaller sizes its area and power dissipation decrease while its speed increases. This is the reason why it became the state of the art device for digital microelectronics nowadays with its ideal characteristics fulfilling, to a good degree, all the points of an ideal logic device. The reliability of the transistors are sought through two parallel ways: the materials study and the introduction of new devices. Digital applications of single electronics include the use of SETs as replacement for the normal transistors in what is known as Single Electron Transistor logic (SET logic). In order to have a three terminal device a gate is coupled to the central island via a capacitor or a resistance. The SET operates

2 95 mainly as a switch and the fact that SETs may exhibit negative transconductance which allows the implementation of complementary circuits using transistors of a single type (K. K. Likharev 1987; J. R. Tucker 1992) there is no N and P-type in metallic SETs. However, direct reproduction of CMOS gates is impossible because SETs cannot be open in as wide a range of gate voltage as the FETs. A discussion of the ultimate performance of the SET and the limits imposed on its operation and geometry is given by Lutwyche and Wada (1994). They concluded by proposing an ideal geometry for SETs and giving a possible planar fabrication process for its realization. A more detailed analysis of specific circuits is presented by Korotkov et al. (1995, 1996). The same group presents a complete set of complementary logic circuits and estimates its maximum operation temperature, switching speed, power consumption, noise tolerances and error rates. They also show how to calculate the parameters margins of the basic gates. Microelectronic systems can be analyzed by various possible approaches at three levels namely device, circuit and systems. Circuit level deals with the solution of linear / non-linear systems of equations by various matrix solution technique, such as nodal analysis. To overcome the cumbersome and error prone problems in different simulators and extraction tools, a device simulator was coupled to circuit simulator such as SPICE. Early SPICE semiconductor model could not model the advanced submicron devices accurately at high speed or high power levels. Later mixed mode simulation can be characterized by the circuit as the function of doping profiles, carrier models, transport models and so on. It becomes more important when analyzing the behavior of advanced submicron devices like Hetero structure Bipolar Transistors (HBTs) or High Electron Mobility Transistors (HEMTs) remarkably if SPICE models are not available. Device modeling in circuit applications faces divergence in accuracy, efficiency and development time.

3 96 Mixed mode simulation in TCAD provides an unique ability to the designers to test and develop complex devices or complex physical events in SPICE (Simulation Program of Integrated Circuits and Emulation) circuit simulation. During research and development of new device structure, it is relatively slow for the device designer to build a custom compact model for each variation. However, physical TCAD device model can be developed ; if once done, mixed mode TCAD simulation test on circuits can be performed to evaluate effectiveness of different design. It includes physical simulation of 2D or 3D semiconductor device. The run time depends on the specific software, complexity of the TCAD device mode and simulation settings. The general run time for the event transient simulation can be expected to run for few hours to few days for a standard analog or digital circuit. The overall run time of TCAD mixed mode device simulation run time is determined by the convergence of TCAD device solver. The advantage of mixed mode TCAD is that initial simulation setup is simple, that enable for quick analysis in new circuit design and technologies. Physics based TCAD modeling tools often requires the designers to convert the existing net list of the circuit to the custom format used in TCAD software, a complicated process. i.e., all tools do not support compact circuits. When scaling the physical structure of the device and its doping profiles for new technology node, easy way to test is by the circuit simulation. However it is meaningless if it gives incorrect or unphysical results. Mixed mode in Sentaurus Device is used to simulate circuits in combination with SPICE models. It also provides mixed mode circuit simulation of multiple device structures simulated using device simulation and compact circuit models. The three most common methods of analysis implemented in circuit simulators are namely DC analysis, transient analysis

4 97 and small signal AC analysis. Transient mode simulation process resolves the device properties at any increment of time. A circuit is often a description of interconnection of its elements. The description can be either developed by textual form using circuit specification language or in graphical format using schematic capture. Sentaurus TCAD performs the circuit simulation based on the textual description of SPICE code. Kirchoff current law (KCL) and Kirchoff voltage law (KVL) are mostly used to translate the connectivity information into the equation relating the electrical variables. Physical responses of the circuit elements for various electrical stimuli can be illustrated with consecutive circuit relations. Each relation is a mathematical model of the actual physical behavior of the element and is characterized by physical parameters such as device operating conditions, width and length of the device and thickness of oxide gate. 6.2 SIMULATION METHODOLOGY OF MIXED MODE IN SDEVICE Figure 6.1 (a) and (b) shows, the SET can act as elementary ON and OFF switch. SET as a switch is possible due to the current carrying electrons which pass the island one by one. The device can be biased at different working points to function as a complementary switch (one turns ON and the other OFF by the same voltage). The voltage swing V defines the different voltage levels representing logic '0' (ground) and logic '1' (VDD). The OFF current is the leakage current causing power dissipation under static conditions. The switching speed is determined by ON current driven through the transistor. The switching property of the device is used to implement the various logic gates for implementing digital circuits.

5 98 Figure 6.1 (a) &(b) Logic gate design using complementary switch 'n' and 'p' (c) Power dissipation under static conditions (d) Fast charging and discharging of the output node. In this chapter transient response of the n-channel and p-channel single electron transistor is obtained using mixed mode device simulation. The simple circuits like NOT, AND, NAND, OR, NOR, 2:1 MULTIPLEXER is simulated using generic SPICE code to verify the logic. The mixed mode simulation allows circuit simulation that combines any number of devices of arbitrary dimensionality (1D, 2D or 3D) with other devices based on the compact models (SPICE). The work deals on transient mode simulation with 2D physical devices, a recessed channel of n-type and p-type single electron transistor combined with a capacitor and a voltage source. The device computes the transient response of various circuits to a voltage signal. The physical devices named NSET and PSET are defined in separate Device statements. The p-channel has twice the area factor of the n- channel SET which is equivalent to setting twice the gate width.

6 99 The circuit is defined in System section where the SPICE syntax is used. The p-channel and n-channel single electron transistor are connected to form a inverter, NAND, NOR, AND, OR, TRISTATE BUFFER and 2:1 MUX circuits along with a capacitive load and voltage source for the input signal. The voltage source is a piecewise linear signal that generates a 010 binary sequence. The Set command defines the nodal voltages at the beginning of the simulation. Output file names, which are not device-specific are defined outside the Device section. The circuit and physical device equations are solved self-consistently for the duration of input pulse. A transient simulation is performed for specified duration time using Transient command. The circuit and contact equations are included with the continuity equation. Finally the simulation results are plotted using Inspect or Tecplot_sv command. From the graphs obtained, the propagation delay of each circuit is calculated to analyze the circuit speed. 6.3 REALIZATION OF LOGIC CIRCUIT USING COMPLEMENTARY SETS The single electron transistor, a basic building block of single electron transistor circuits is considered to be an eventual limit of electronic circuits in which the change of one electron level can represent a logic level. The SET circuits are configured similar to CMOS circuits, the pull up transistor (p-channel) tied to VDD and the pull down transistor, usually a n- channel transistor tied to ground. The single electron transistor has only a single gate terminal. The dimensions and the doping concentration of p- channel transistor is from Table 5.1. The n-channel is also constructed with the same dimensions as that of p-channel SET as shown Table 6.1.

7 100 Table6.1 Details of regions for the proposed n-channel structure Buried Source/ Region Substrate Gate Spacers Channel Oxide Drain Materials used Doping concentration Silicon Silicon with Silicon Poly Silicon with Phosphorous di oxide Silicon Nitride boron doping doping Silicon with Phosphorous doping 1 e e e +16 Dimensions 10 10nm nm nm 2 1 2nm 2 4 1nm nm Single Electron Inverter When two complementary biased single electron transistors are pulled together, SET inverter structure can be obtained as shown in Figure 6.2. The p-channel transistor is pulled up to VDD (supply) and the other transistor is tied to the ground. Figure 6.2 Schematic of inverter circuit

8 101 Figure 6.3 Output of inverter under static conditions for the recessed channel SET Figure 6.3 shows the simulation output of the inverter. The output switches from low to high for the terminal input voltage of high to low, by passing the electrons to the load capacitance at the output. The rise time and fall time of the input voltage is assumed as seconds. Propagation delay of 3 picoseconds (ps) is observed at output Single Electron NAND Circuit The two input NAND gate logic is constructed by connecting n- channel SETs (N-SETs) in series and p-channel SETs (P-SETs) in parallel as shown in Figure 6.4. When both the inputs are HIGH, the N-SETs are active and hence the output degrades to zero as output is pulled to ground by the transistors. If any one of the inputs or both are LOW, the output is pulled to VDD by the active P-SETs which are parallel.

9 102 Figure 6.4 Circuit diagram of NAND logic The output as in Figure 6.5 is generated after a delay of 7ps due to more number of transistors. The propagation delay is twice than that of the inverter circuit. Figure 6.5 Verification of logic output for two input NAND gate

10 Realization of NOR Circuit The action neither of two inputs NOR as shown in Figure 6.6 can be explained as follows. Here the P-SETs are in series and N-SETs are connected parallel to understand the logic function of NOR. When both inputs (Vin1 and Vin2) are LOW, the upper transistors connected to VDD is ON and the lower transistors are turned OFF. Hence at initial condition, the tunnel capacitors are charged that result in HIGH output. When any one input (Vin1 or Vin2) is low, the OFF condition of a P-SET switch makes an open circuit. Therefore, the charge stored in load capacitance discharges to ground through the N-SET switch making the output LOW. Figure 6.6 Illustration of two input NOR gate using SET

11 104 Figure 6.7 Realization of NOR output for inputs Vin1 and Vin2 Similarly, when the inputs Vin1 and Vin2 are HIGH, the P-SETs are turned OFF and pull down switches (N-SETs) are ON making the output to held at LOW as shown in Figure 6.7. The propagation delay of the circuit is 9ps which is three times larger than the delay of inverter circuit. Hence the speed of the circuit decreases due to resistive drops in pull up transistors that connected in series increases Realization of AND/OR Circuit Using Universal Gates When the output of NAND and NOR gates are fed to an inverter circuit, AND gate and OR gate can be recognized respectively as shown in Figure 6.8. The operation of the device is similar to logic gates explained above.

12 105 (a) Figure 6.8 (b) Schematic diagram of (a) AND, (b) OR logic using NAND, NOR circuit respectively

13 106 (a) Figure 6.9 (b) Familiarization of AND gate & OR gate using NAND & NOR respectively

14 107 The output waveform of AND gate and OR gate is shown in Figure 6.9. The propagation delay of the AND gate and OR gate increases to 20ps and 28ps respectively including the charging and discharging effects of load capacitance Tristate Buffer A gate capable of being in '1', '0' and tristate is called tristate gate is shown in Figure Tristate means a state of logic other than '0' and '1' in which there is high impedance state. Complementary p-channel and n-channel Figure 6.10 Schematic of tristate buffer with truth table Figure 6.11 Output realization of tristate buffer

15 108 SET pair as bidirectional current flow symmetrical switch. From the Figure 6.11, the output waveform of the tristate buffer deduce that for inactive enable input, high input impedance state is determined which is neither logic '0' nor logic '1'. For active enable input, the input is transmitted to the output. The output is delayed due the presence more number of transistors :1 Multiplexer Figure 6.12 Schematic of the 2:1 Multiplexer using single electron transistors. A multiplexer is a combinational circuit that selects any one of the input lines and directs it to the output i.e., it requires 'n' select lines for 2 n input lines. It is also called a data selector since it selects one of many inputs and steers the binary information to the output line. The 2:1 multiplexer is constructed as shown in Figure It has two stages: the first stage has the inverted multiplexer stage and the second stage has the inverter stage. In multiplexer stage the select line is zero, the input Vin1 is selected otherwise

16 109 Vin2. In the second stage, the inverted output of multiplexer stage is simply inverted. Thus it causes some delay between input and output. Figure 6.13 Output of 2:1 multiplexer Figure 6.13 shows the output of the 2:1 multiplexer. When the select line is low, input1 is selected to the output. The input2 is selected only if the select line triggers from low to high. The rise time and the fall time of both the inputs and select lines are 1 picosecond. The output of multiplexer takes nearly 20 picoseconds to settle in high state.

17 SUMMARY In this study, we developed the physics based compact model using Sentaurus TCAD Mixed Mode Simulation. The logic gates and circuits are constructed which are suitable for transient simulation. The propagation delay for each circuit is also obtained. The propagation delay depends on the (series or parallel) connection of transistors. The simulation time is more for complex circuits, a disadvantage of mixed mode simulation of TCAD i.e., it runs more than a day to converge the output.

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