ENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph

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1 ENG2410 Digital Design CMOS Technology Fall 2017 S. reibi School of Engineering University of Guelph

2 The Transistor Revolution First transistor Bell Labs, 1948 Bipolar logic 1960 s Intel 4004 processor Designed in 1971 lmost 3000 transistors Speed:1 MHz operation 2

3 Transistors Can be classified as: BJT Bipolar Junction Transistor; Bipolar device (two carriers) Current controlled device FET Field Effect Transistor; Unipolar device (single carrier) Voltage controlled device 3

4 Logic Families RTL, DTL earliest TTL was used 70s, 80s Still available and used occasionally 7400 series logic, refined over generations CMOS Was low speed, low noise Now fast and is most common BiCMOS and Gas Speed 4

5 CMOS Technology

6 Semiconductor Materials o o o Electronic materials generally can be divided into three categories: Insulators Semiconductors Conductors The primary parameter used to distinguish among these materials is the resistivity (rho) Insulator 10 5 < rho Semiconductors 10-3 < rho < 10 5 Conductors rho < 10-3 Silicon and germanium are the most important semiconductor materials 6

7 P-type and N-type o o The real advantage of semiconductors emerge when impurities are addedto the material in minute amounts (Doping) Impurity doping enables us to change the resistivityover a very wide range and determine whether the electron or hole population controls the resistivity of the material. Donor Impurities: have five valence electrons in the outer shell (phosphorus and arsenic). Semiconductors doped with donor impurities are called n-type. cceptor Impurities: have one less electron than silicon in the outer shell (boron). Semiconductors doped with acceptor impurities are known as p-type. 7

8 MOSFET: Metal Oxide Semiconductor Field Effect Transistor voltage controlled device Dissipates less power chieves higher density on an IC Has full swing voltage 0 5V 8

9 The MOS Transistor Polysilicon luminum 9

10 nmos Transistor n nmos Transistor I ds V GS V gs 10

11 Transistor as a Switch Switch! n MOS Transistor V GS V T V GS S Ron D 11

12 Implementing Logic using: nmos vs. pmos Devices 12

13 Complementary MOS (CMOS) OFF ON In1 In2 V DD PUN PUN and PDN are dual logic networks PMOS only OFF ON InN In1 In2 InN PDN NMOS only F(In1,In2, InN) V SS t every point in time (except during the switching transients) each gate output is connected to either V DD or V SS via a low resistive path 13

14 CMOS:Complementary MOS Means we are using both N-channel and P-channel type enhancement mode Field Effect Transistors (FETs). Why?

15 Threshold Drops Use PMOS Transistors in Pull Up Network PUN V DD S V DD D Strong 1 V DD Weak 1 D 0 V DD V GS S 0 V DD - V Tn C L C L PDN V DD 0 V DD V Tp VDD D C L Strong 0 V GS S C L Weak 0 S D Use NMOS Transistors in Pull down Network 15

16 Complementary MOS (CMOS) o NMOS Transistors pass a ``strong 0 but a ``weak 1 o PMOS Transistors pass a ``strong 1 but a ``weak 0 o Combining both would lead to circuits that can pass strong 0 s and strong 1 s C X C 16

17 CMOS Inverter 0 1 V DD Pull-up Network GND Pull-down Network 17

18 CMOS Inverter V DD OFF =1 =0 ON GND 18

19 CMOS Inverter V DD ON =0 =1 OFF GND 19

20 CMOS Tri-State Inverter E 0 X Z E E 20

21 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high B In Series X = X if and B In Parallel X B = X if OR B NMOS Transistors pass a strong 0 but a weak 1 21

22 PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low B In Series X = X if ND B = + B In Parallel X B = X if OR B = B PMOS Transistors pass a strong 1 but a weak 0 22

23 Example Gate: NND B X = X if an d B X B = X if O R B N M O S T r a n sistors p a ss a str ong 0 b u t a w e ak 1 Pull Down Network 23

24 Example Gate: NND PMOS switch closes when switch control input is low B X = X if ND B = + B X B = X if OR B = B PMOS Transistors pass a strong 1 but a weak 0 Pull Up Network 24

25 Example Gate: NND 25

26 Example Gate: NOR B X = X if an d B X B = X if O R B N M O S T r a n sistors p a ss a str ong 0 b u t a w e ak 1 26

27 Construction of Compound Gates Example: Step 1 (n-network): Invert F to derive n-network Step 2 (n-network): Make connections of transistors: ND Series connection (.B). (C.D) OR Parallel connection ((.B) + (C.D)) 27

28 Construction of Compound Gates Example: Step 1 (n-network): Invert F to derive n-network Step 2 (n-network): Make connections of transistors: ND Series connection (.B) series, (C.D) also in series OR Parallel connection ((.B) + (C.D)) in parallel 28

29 Construction of Compound Gates (cont d) Step 3 (p-network): Expand F to derive p-network each input is inverted Step 4 (p-network): Make connections of transistors (same as Step 2). 29

30 Construction of Compound Gates (cont d) Step 3 (p-network): Expand F to derive p-network each input is inverted Step 4 (p-network): Make connections of transistors (same as Step 2). Step 5: Connect the n-network to GND (typically, 0V) and the p-network to VDD (5V, 3.3V, or 2.5V, etc). 30

31 Complex CMOS Gate B C D D B C OUT = D + (B + C) 31

32 CMOS Properties There is always a path from one supply (VDD or GND) to the output. There is never a path from one supply to the other. (This is the basis for the low power dissipation in CMOS virtually no static power dissipation.) There is a momentary drain of current (and thus power consumption) when the gate switches from one state to another. Thus, CMOS circuits have dynamic power dissipation. The amount of power depends on the switching frequency. 32

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