Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM
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![[ 2007 International Conference on VLSI Design ] Jan.](/docs-images/89/98689702/images/1-0.jpg "9, 2007 Ultra Low Voltage Operation with Bootstrap Scheme for Single")
1 [ 2007 International Conference on VLSI Design ] Jan. 9, 2007 Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, *Akira Tada, *Takashi Ipposhi Kobe University, Kobe, Japan *Renesas Technology, Hyogo, Japan
2 2 Outline 1. Background and Goal 2. Active Body-Biasing Controlled (ABC)-SOI for Bootstrap Scheme 3. SOI-SRAM with Bootstrap Scheme 4. Simulation Results 5. Summary
3 3 1. Background and Goal Memory crisis by aggressive scaling down Scaling process technology down for SRAM included - Higher performance - Larger memory capacity - Lower power consumption Achieved at the same time so far These are significant challenges in deep sub-micron era mainly due to restricted supply voltage reduction
4 1. Background and Goal Difficulties of SRAM in ultra low voltage operation Simply lowering supply voltage to sub-1v causes: (1) Degradation of static noise margins (SNM) Solution: Additional transistors avoiding cell-data destruction (e.g. 8T-SRAM / 7T-SRAM) (2) Exponential increase in access time Solution: Boosted word line (WL) Enhances cell-current in both read/write mode 4
5 1. Background and Goal Our goal Shortening access time even in sub-1v operation by boosted WL scheme with single power supply BL /BL WL I write I Iread 6T-SRAM cell-current of access Tr can be increased 5
6 2. ABC-SOI for Bootstrap Scheme ABC (Active Body-biasing Controlled) - SOI Direct body contact N + P - Gate N + Gate Buried P + N Oxide - Si Substrate Hybrid Trench Isolation SOI MOSFET Body Each body voltage can be dynamically controlled through direct body contact without area penalty 6
![2. ABC-SOI for Bootstrap Scheme ABC-SOI Capacitor ABC-SOI enhances capacitance between gate and source/drain Capacitance [ff] C GS Source Body-tied SOI capacitor 60 50 40 30 20 10 0 Gate ABC-SOI](/docs-images/89/98689702/images/7-0.jpg "C GD Drain W=20um W=10um C GS C S-body ABC-SOI capacitor Body-tied SOI 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.")
7 2. ABC-SOI for Bootstrap Scheme ABC-SOI Capacitor ABC-SOI enhances capacitance between gate and source/drain Capacitance [ff] C GS Source Body-tied SOI capacitor Gate ABC-SOI C GD Drain W=20um W=10um C GS C S-body ABC-SOI capacitor Body-tied SOI Gate voltage (V gs ) [V] C GD C D-body Effective for strong capacitive coupling 7
8 8 3. SOI-SRAM with Bootstrap Scheme WL driver with ABC-SOI capacitor Single boost Tr. WL WL Double stages of boost Tr. Isolation Transmission transistor transistor Delay circuit V WL C BS (W BS ) BL 0 BLB 0 BL 1 BLB 1 BL 2 BLB 2 ABC-Boost transistor for capacitive coupling C BS /2 (W BS /2) BL 0 BLB 0 BL 1 BLB 1 BL 2 BLB 2 WL V V WL Pulsed WL tt Memory Cell
9 3. SOI-SRAM with Bootstrap Scheme Boosting effect of WL voltage (V WL ) Capacitive coupling by boost Tr. decides V WL C BS C total V WL = 1 + C BS V DD WL V WL C BS : Cap. of Boost Tr. C total : Total cap. of WL node C BS C WL : Boost Tr. Parameter conditions: C total = C BS + C WL C BS = 7 ff@ W BS = 10um 14 ff@ W BS = 20um C WL = 1.25 ff/cell V WL /V DD W BS = 20um W BS = 10um Bit (# of memory cells in each row) 9
10 4. Simulation Results HSPICE simulation setup Process Supply voltage Threshold voltage SRAM configuration Transistor size Area penalty 0.18um PD-SOI V DD = 0.35 ~ 0.6V V th-n / V th-p = 0.35 / -0.42V () V th-n / V th-p = 0.24 / -0.34V (peripheral) 8k-bit (256word x 32bit), 6T-SRAM W = 0.5um () W = 5um (WL driver) W = 20um (Boost Tr.) 26% (Inclusive of 32bit/row + WL driver) 10% (whole memory array) 10
11 Time [s] Time [s] Simulation Results Access time Improvement of Write: 34% Read: 37% (V DD = 0.4V) Voltage [V] WL(conv.) CK Write mode WL(prop.) 29.1ns 19.3ns Voltage [V] Access time [ns] conv prop. WL(conv.) Supply voltage [V] Read mode 82.5ns WL(prop.) 131ns Read Write BL(conv.) BL(prop.) conv. prop. Data node(conv.) Data node(prop.) CK BL out (prop.) BL out (conv.)
12 4. Simulation Results V th dependence of access time Access time [ns] x 1.53x Write Read 1.99x 1.21x conv. prop. conv. prop. V DD = 0.5 V V th0 = 346 mv % 3% V th0 +3% +10% Threshold voltage (V th ) [mv] t access (worst) t access (best) = 2.54 (conv.) 1.53 (conv.)
13 13 4. Simulation Results Power saving effect Power consumption [nw] prop. 0.80x 0.74x conv. 0.70x Access time [ns] Power comparison at same operational speed
14 5. Summary *ABC: Active Body-biasing Controlled 14 Ultra low voltage operation for SRAM Degradation of static noise margins (SNM) 8T / 7T-SRAM will be effective Exponential increase in access time Boosting WL by *ABC-SOI capacitor - Strong capacitive coupling is achieved by body capacitance in ABC-SOI - Access time reduction of 34%@Write, 37%@Read - Smaller impact of V th variation on access time
15 15
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