CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM

Transcription

1 131 CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM 7.1 INTRODUCTION Semiconductor memories are moving towards higher levels of integration. This increase in integration is achieved through reduction in storage cell size causing a reduction in the charge representing a stored bit. This raises the reliability issues of memories (Andrei Pavlov and Manoj Sachdev 2008). Moreover, memories occupy the largest area in modern ICs. Hence the drastic device shrinking with higher operating speeds reduce the reliability of deep submicron ICs. When memories (SRAM) are used in critical applications like space, the main cause for reliability reduction is due to soft errors also called as single event upsets (SEUs), which are radiationinduced transient errors caused by neutrons from cosmic rays and alpha particles from packaging materials. Errors occurring in SRAMs can be hard or soft (transient) errors. Hard errors are the permanent faults that cannot be overcome by rewrite operation. Structured scan-based and BIST techniques are effective means to detect permanent faults (Ashok Sharma 2004). Soft errors are due to heavy particles incident on sensitive node of the SRAM producing electron-hole pairs, and this ionization can cause flip on data (Srour and McGarrity 1988, Sherra Kerns and Shafer 1988). Thus, soft error is a potential threat to the reliability of memories in space environment (Pickel and Blanford 1978, Thomas Turflinger and Martin Davey 1990).

2 132 Traditionally soft errors are regarded as a major concern only for space applications. But for designs manufactured at deep submicron technology, soft errors are more frequent due to the alpha particles created by unstable isotopes found in the packaging materials of a chip. Hence soft errors occur not only at space environment, but also occur at the ground level (Mitra et al 2005, Michael Nicolaidis 1999). Thus designing of soft error tolerant SRAMs gains importance. 7.2 LITERATURE SURVEY Soft errors can be overcome by various methods such as hardening, protection and recovery. Hardening technique uses insertion of transistors like duplicating, to make the cell insensitive to single event upsets (Calin et al 1996). The main drawback of the work done by Calin et al (1996) is, it uses 12 transistors for each memory cell, increasing the area by twice. Protection method (Shiyanovskii et al 2008) uses capacitor, which is vertically connected between two storage nodes (Q QBAR) of SRAM cell. When particle due to radiation, strikes on sensitive node of the SRAM cell, the capacitor gets charged. But this method is applicable only when memory is at standby condition. If protection method is used under operating condition, it will increase the access time. Recovery method uses error detection and correction principle. To maintain the acceptable reliability levels of SRAM, Error Correcting Codes (ECC) are often used to detect and correct soft errors often called as Single Event Upset (SEU). But ECC may cause area overhead, and significant performance and power dissipation. This technique detects and corrects the error only while reading the faulty bit. So there will be latency between the occurrence of the SEU and correction, which can cause accumulation of SEUs. These drawbacks can be overcome by using Built In Current Sensor (BICS) to detect soft errors. Traditional BICS (Nicolaidis et al 1993, Vargas

3 133 et al 1993) are used to monitor the static current dissipation on the circuit, which is synchronous in nature. On the other hand SEU can occur at any instant of time. To cope with these problem, asynchronous BICS are used (Vargas and Nicolaidis 1994), which has asynchronous latch. This BICS is connected on the vertical power lines of a memory to find the faulty column. Parity bit per memory word was used to find the faulty row, in such a way that it can detect the affected bit and will perform the error correction. The BICS used is asynchronous one. This makes the BICS design more difficult than synchronous BICS. The BICS proposed by calin et al (1995) has more voltage drop in V DD and gnd. It is overcome by BICS proposed by Balkaran Gill et al (2005), where only single cell is considered for a column which results in the voltage drop of less than 10mV. But it cannot detect the soft error under operating condition. The aim of this chapter is to propose a BICS, which detects the soft error under both operating and standby condition without affecting the performance of the BICS. All the simulations have been carried out using T-SPICE in 90 nm technology. 7.3 RADIATION EFFECT ON SRAM CELL Sources of radiation Memory performances are severely affected by the radiation particles. These charge particles are present in the space environment as cosmic rays and they are present within the chip as -particles. The -particle is caused by the radioactive decay of uranium and thorium impurities present in the chip packaging materials and interconnects of the chip Single Event Upset in SRAM Single Event Upset (SEU) in memories refers to the loss of information from a memory cell caused by a single ionizing particle. The

4 134 effect of SEU in a SRAM cell is the flip of data from 0 to 1 or 1 to 0. When a single high energy particle strikes the sensitive nodes of the SRAM cell, the charge generation and collection occurs as shown in Figure 7.1. Figure 7.1 Particle strike and charge generation The two sensitive nodes in the SRAM cell are the drain of the OFF_NMOS and the drain of the OFF_PMOS. The drain of the OFF_MOS transistors forms the reverse biased PN junctions with the substrates. These junctions are more sensitive to particle strikes and will cause the generation of electron and hole pairs, when the particle passes through the PN junction. The generated electrons move towards the positive voltage of reverse biased junction and holes move toward the negative voltage side. These movement of charges cause the generation of current pulse at the sensitive nodes of the cell. Thus when a particle strike occurs, a current pulse as shown in Figure 7.2 is generated at the sensitive nodes of the SRAM cell, causing the data stored in the cell to flip. The memory cell flips the data, when collected charge exceeds the critical charge (Q crit ) that has been stored in the sensitive node, where the critical charge Q crit is the minimum charge required to flip the data.

5 135 Figure 7.2 Current pulse generated due to particle strike The critical charge not only depends on the charges collected at the struck node, but also depends on the current pulse produced at the same node. This current pulse is equivalent to the current between drain and the substrate. 7.4 SRAM SOFT ERROR In CMOS circuits SEUs are modeled by injecting the current pulses as shown in Figure 7.2, at the sensitive nodes. The current pulse has fast rise time and gradual fall time. The shape of current pulse is approximated by Equation 7.1 -t -t c tf tr I (t) = (e - e ) Q t -t (7.1) f r where Q c is the charge collected due to particle strike, t r is the rise time and t f is the fall time (Balkaran Gill et al 2005). Figure 7.3 shows the conventional

6 136 6T SRAM cell designed at 90nm process technology with operating voltage of 1.05V having two sensitive nodes Q and QBAR. BL V DD BLB WL P1 P2 N3 Q WL QBAR N4 N1 N2 Figure 7.3 SRAM Cell structure Soft error under standby condition The soft error can occur at any instant of time. When the SRAM is under standby condition, a 1 to 0 flip is said to occur when the particle strikes and discharges the charge stored at the drain of the OFF_NMOS transistor. Similarly a 0 to 1 flip is said to occur when the particle strikes and discharges the drain of the OFF_PMOS transistor. For analysis, a current pulse with fast rise time and gradual fall time is generated by choosing t r = 5ps and t f = 370ps. It is injected at the OFF_NMOS transistor (N1) of the SRAM cell shown in Figure 7.3.

7 137 Figure 7.4 SRAM soft error under standby condition Figure 7.4 shows the simulation result of SRAM cell for the injected current pulse at standby condition. From 0 to 10 ns word line (WL) is enabled during which bit line (BL) remains high and Bit line bar (BLBAR) remains at 0. Hence the nodeq has the value 1 and QBAR 0 as shown in Figure 7.4

8 138 At 15 th ns, when the current pulse is injected at nodeq, the data gets flipped from 1 to 0 at nodeq and from 0 to 1 at nodeqbar indicating the occurrence of soft error Soft error under operating condition Figures 7.5, 7.6 and 7.7 indicate the occurrence of soft error under operating conditions. Figure 7.5 shows that the data flip does not occur when the current pulse is injected at the intermediate time of write operation. From 0 to 10 ns data 1 is written, hence WL is high, Q is 1V and QBAR is 0V. Current pulse is injected during write operation at 5 th ns. Q remains at 1V and QBAR at 0V; hence there is no flip of data. Figure 7.5 No flip under intermediate time of write operation

9 139 Figure 7.6 shows that the data gets flipped (Q becomes 0V and QBAR becomes 1V) when current pulse is injected at the end of write operation at 9.7 th ns. Figure 7.7 shows the flip of data when the current pulse is injected during read operation. From 0 to 10ns data 1 is written and from 10 to 20ns data 1 is read. Hence WL remains high till 20ns and Q is at 1V and QBAR is at 0V till 10ns. When the current pulse is injected during read operation at 15 th ns, Q becomes 0V and QBAR shifts to 1V resulting in flip of stored data. Figure 7.6 Flip at the end of write operation

10 140 Figure 7.7 Data flip during read operation 7.5 EXISTING BUILT IN CURRENT SENSOR Figure 7.8 shows the BICS proposed by Balkaran Gill et al (2005). It uses current mirror and current source load inverter to amplify the upset current pulse and convert it into logic level voltage pulse. In Figure 7.8, S VDD is formed using transistors M v1 to M v8. S VDD is a 1 to 0 flip detector which detects and amplifies a transient current pulse generated due to 1 to 0 flip and provides logic level voltage pulse. S gnd is formed using transistors M G1 to M G8 and is a symmetrical counterpart of S VDD. It is used to detect 0 to 1 flip. Both S VDD and S gnd provide logic level voltage pulses (E v and E g ) when flip occurs and that is used to set an asynchronous latch. If any one of the two

11 141 outputs goes high then the latch is triggered and it generates the error signal Err 1. The BICS provides V DD and gnd to the column of the SRAM array. S VDD V DD VV DD dd V DD V DD dd B v B g V DD Reference Voltage Generator V DD V DD V DD V DD Figure 7.8 BICS proposed by Balkaran Gill et al (2005) Transistors M v1 and M v2 form an n-channel current mirror and transistors M v7 and M v8 form a current source load inverter. M v5 and M v6 act as the source resistors for the current mirror. The source current for the current mirror and current source load inverter is provided by transistors M v3, M v4 and M v8. The biasing voltage for transistors M v3, M v4 and M v8 are provided by reference voltage generator circuit as shown in Figure 7.8. It is a simple CMOS voltage divider that provided two levels of biasing voltages, B v

12 142 and B g for S VDD and S gnd respectively. The reference voltage generator is used for ensuring the correct BICS operation under power supply variations. It decreases or increases the output biasing voltage, when V DD decreases or increases. B v in S VDD is low making the transistors M v3, M v4 and M v8 to be turned ON. This allows the current drawn from V DD to reach the current mirror circuit. When a particle strikes at the drain of OFF_NMOS transistor of the SRAM cell, a transient current pulse is produced at the struck node. The current (I V ) flows from V DD to the struck node through the ON_PMOS transistor. When I V flows from V DD to the struck node, the current through the transistor M v1 decreases. As the transistors M v1 and M v2 forms a current mirror, the current through M v1 is mirrored through M v2 resulting in a reduced current through M v2. This causes an increase in the drain voltage of the transistor M v2. As the drain of the transistor M v2 is connected to the gate of the transistor M v7, it is turned ON. This results in a reduced voltage at the drain of M v7. This voltage is inverted to get full logic value at node E v by using the transistors M v9 and M v10. Similarly S gnd produces a full logic value at node E g, when particle strikes at the drain of the OFF_PMOS transistor of the cell. The outputs E v and E g are the inputs to the asynchronous latch. If any of the two outputs goes high then the latch is triggered and it will generate the error signal Err 1. When E v is high M1 transistor is turned ON and when E g is high M2 transistor is turned ON. For both the condition the node voltage N1 becomes low and hence node voltage N2 becomes high (back to back connected inverter). Thus the error signal Err 1 is generated. The reset signal (RST) is used to reset the asynchronous latch, after the upset is detected and during write and read operation. The signals Bypass V DD and Bypass gnd are used to disable the BICS operation during memory write and read operations. Hence this BICS is capable of detecting soft error only during standby condition but Figure 7.7

13 143 and Figure 7.8 indicates the occurrence of soft error during operating conditions also. Hence, a novel BICS is proposed in this chapter which is capable of detecting soft error at both standby and operating conditions. 7.6 PROPOSED BUILT IN CURRENT SENSOR Figure 7.9 shows the proposed BICS. In addition to S VDD, S gnd and asynchronous latch, a delay element with NMOS and PMOS transistors has been added as shown in Figure 7.9. S VDD, S gnd and asynchronous latch operates the same way as the existing BICS (Balkaran Gill et al 2005). But the signals Bypass V DD and Bypass gnd are not used in proposed BICS because the memory column is monitored for SEU during read and write operation of memory also. Figure 7.9 Proposed BICS

14 144 To enable the BICS operation under operating condition, the logic circuitry with delay element is used. This circuit is used to control the reset signal for all operating conditions. The reset control circuit contains one delay element and the transistors R p1, R p2, R n1, R n2 and R 3 as shown in Figure 7.9. The input to the delay element is word line (WL) signal. The delay element delays the WL signal when it is enabled during write operation. Buffer is used as the delay element and the buffer is designed to have the required delay. For the designed SRAM the write time is 10ns, so the required delay is considered as 8.5ns. The buffer is designed to obtain 8.5ns delay in such a way that the reset signal is enabled for first 8.5ns during write operation. The delayed signal is then given to the transistors R p2, R n2 and the WL signal is given to transistors R p1, R n1 to disable the reset signal during write operation. Similarly read enable signal (Read) is connected to the gate of the transistor R 3 to disable the reset signal during read operation. During standby condition, WL is in logic 0', R p1 is ON, so node a gets discharged and reset signal goes to logic 0 and BICS will be in operation. Hence if any flip occurs, error signal will be generated. During read operation, in addition to WL signal, read enable signal (Read) is also enabled so transistor R 3 is switched ON, node a gets discharged and reset signal becomes logic 0 enabling the BICS to generate error signal. Similarly during write operation, WL signal is high and the delayed output is low for first 8.5ns, turning ON the transistors R n1 and R p2. Thus node a remains at V DD, reset signal is in logic 1 disabling BICS for first 8.5ns. After a delay of 8.5ns the delayed WL signal remains high, turning OFF the transistor R p2 and turns ON R n2. Thus node a gets discharged making the reset signal low and enables the BICS operation at the end of write cycle (last 1.5ns). So BICS is ON for the entire period of standby condition, read operation and at the end of the write operation.

15 SIMULATION RESULTS AND DISCUSSION Figure 7.10 shows the simulation result of the proposed BICS during standby condition. WL signal remains high for 10ns during which data 1 is written into the cell making nodeq high. When the current pulse (I) is injected at 15 th ns (standby condition), the data gets flipped (Q becomes 0 and QBAR becomes 1 ). This upset is detected by the proposed BICS and makes the error signal (Error) high. Figure 7.10 BICS detection of soft error under standby condition

16 146 of write operation. Figure 7.11 shows the simulation result of 1 to 0 flip at the end Figure 7.11 BICS detection of soft error at the end of write cycle WL signal remains high for 10ns during which data 1 is written into the cell making the nodeq high. When the current pulse (I(Q)) is injected at 9.3 rd ns, the data gets flipped (Q becomes 0 and QBAR becomes 1 ). The nodee V in the proposed BICS is one of the inputs to the asynchronous latch to

17 147 generate the error signal (ERROR). The signal RST becomes low after 8.5ns during which the error signal is generated at the end of write operation. Figure 7.12 BICS detection of soft error during read cycle Figure 7.12 shows the simulation result of 1 to 0 flip during the read cycle. From 0 to 10ns, data 1 is written and from 10 to 20 ns, data 1 is read. So, WL remains high for 0 to 20ns. The current pulse is injected during read operation at 15 th ns as shown in Figure Hence at 15 th ns the data gets flipped (Q becomes 0 and QBAR becomes 1 ). The nodee V in the proposed BICS which is the input to the asynchronous latch, goes high. This makes the

18 148 generation of the error signal (ERROR) during the read operation when WL signal remains high as shown in Figure Table 7.1 and Table 7.2 show the various simulations done at the end of write cycle and during read cycle respectively, for different charge and different fall time with the rise time t r kept constant at 5ps. The first column shows the amount of collected charge, Q. For every value of Q, fall time t f is varied between 100ps and 500ps using a step of 100ps and t r is fixed to be 5ps. The rise time t r could be varied from 2ps to 6ps to make sure that all practical situations are covered, but the variation of t r in such a narrow range does not affect the results. The NF, ND in Table 7.1 and Table 7.2 shows the case when a particle hits a cell but the cell does not flip its content and the particle hit is not detected. The F, D shows the case when a particle striked, flips the cell content and detected by the proposed BICS. There was no case found for the condition that current pulse flipping the cell content but the BICS do not detect the flip. Thus, the proposed BICS scheme is very efficient for SEU detection, as all the flips are detected. Table 7.1 Simulation results for write time soft error Charge Delay time t f (ps) Q (pc) F,D F,D NF, ND NF, ND NF, ND 2.5 F, D F, D F, D NF, ND NF, ND 3.0 F, D F, D F, D F, D NF, ND

19 149 Table 7.2 Simulation results for read time soft error Charge Delay time t f (ps) Q (pc) F, D NF, ND NF, ND NF, ND NF, ND 0.5 F, D F, D F, D NF, ND NF, ND 0.75 F, D F, D F, D F, D NF, ND where F, D is flip and detected condition respectively NF, ND is No flip and no detection condition respectively 7.8 CONCLUSION In this chapter, a BICS design is proposed, capable of detecting soft errors during standby and operating conditions. Simulation results indicate the occurrence of soft error at the end of write cycle and at the intermediate time of read cycle in addition to standby condition. The proposed BICS design with a delay block and internal reset signal generation is capable of turning ON the BICS during the required operating conditions. This makes possible the detection of soft error at any instant of time of its occurrence irrespective of standby or operating condition.