Design of Soft Error Tolerant Memory and Logic Circuits
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1 Design of Soft Error Tolerant Memory and Logic Circuits Shah M. Jahinuzzaman PhD Student Graduate Student Research Talks, E&CE January 16, 2006
2 CMOS Design and Reliability Group
3 Outline What is soft error Soft error sources and mechanism Soft error in logic circuits Soft error in memories Effect of technology scaling on soft error Mitigation techniques Summary
4 What is Soft Error? Transient data upset due to particle strike 1 0 or Minimum charge required for an upset Q crit No damage to hardware - REWRITE or RESET can restore the changed data Random in time and space Affects: latches, flip-flops, memory blocks, and even combinational logic circuits
5 Soft Error Rate Typically expressed in FIT (failure in time) 1 FIT=1failure/10 9 device-hr Sum of typical hard failure rates FIT (oxide breakdown, latch-up etc.) Soft failure rate in unprotected chip 50,000FIT Critical reliability concerns: microprocessors with large cache (e.g., in servers), SRAM based FPGAs and ASICs, aircraft controllers, space-borne electronics, life-support devices such as cardiac defibrillators Source:
6 Sources of soft error High energy (~MeV) particles Alpha particles (~ 4-9 MeV) Cosmic neutrons (~ MeV) and Thermal neutron and 10 B in Borophosphosilicate glass (BPSG) Only 3.6eV is required to create 1 EHP in Si BPSG is no more a concern after 0.25μm tech Alpha particles come form chip packaging materials Neutrons come from cosmic rays and are ever present (background radiation)
7 Alpha Particle Doubly ionized 4 He 2+ atom Sources: Pb in solders and U, Th in IC packaging materials; major concern - solder balls in flip-chip package Penetrates 25μm in Si Can be shielded by epoxy layer (not in flip-chip)
8 Comes from sun or inter-galactic rays Generates EHP indirectly through Si recoil Cannot be shielded: 1ft concrete can lower neutron flux only by 1.4x Cosmic Neutron
9 Relative Influence of SE Sources Alpha particle deposits 4-16 fc/μm Neutron (Si recoil) deposits fc/μm Rate limiting SE source in scaled down devices with high purity materials: cosmic neutron
10 Basic Mechanism of SE R. Baumann, IEEE Design and Test of Computers, pp , May-June 2005 Q coll =ηq dep, η being collection efficiency Q coll generates current transient Q coll depends on doping, collection volume, node voltage, carrier mobility etc. Q coll >Q crit soft error
11 Soft Error in Logic Circuits Also referred to as Single Event Transient (SET) Less troublesome - less density compared to memories and activity dependent Naturally masked by three mechanisms Logical masking Electrical masking Latching window masking Increasing concern with scaling (90nm, onward) Robust enterprise platforms in sub-65nm technologies require design with built-in logic soft error protection, S. Mitra, Intel Corp.
12 Logical Masking Struck node has to be in controlling state for a transient to pass from input to output Output does not depend on B; A is in controlling state A B NAND In order for an error to propagate, there must be a sensitized path along the logic chain
13 Electrical Masking Digital circuits have finite bandwidth and rise-fall time. Transients with bandwidths higher than the cutoff frequency will be attenuated (amplitude, rise and fall time ) and eventually the transients will disappear.
14 Latching Window Masking A transient cannot be latched into a FF/register unless it occurs within the clock window Transient is not latched Transient has to occur here to be latched
15 Soft Error in Memories No masking effects, high density Most susceptible to soft error Memories to consider: Main memory (DRAM) Cache memory (SRAM) Soft error changes the stored bits may lead to catastrophic failures of microprocessors, SRAM based FPGAs etc.
16 Soft Error in DRAM Higher capacitance (3D, trench like), smaller charge collection area, periodic refresh decreasing bit error rate, constant system error rate Word lines Bit lines Trench capacitors Poly word line Metal bit line Trench capacitors R. Baumann, IEEE Design and Test of Computers, pp , May-June 2005
17 Soft Error in SRAM Larger area per bit than DRAM, signal charge stored by two cross-coupled inverter Two nodes are prone to particle hit: one node is more sensitive Critical reliability issue
18 Scaling Trends of SE Signal charge is reduced: Q=CV, both C and V are scaled Particles with lower energy can cause soft error System SER in Semiconductor Memory (FITs) Source: Semico Research Inc. (June 2002) R. Baumann, IEEE Design and Test of Computers, pp , May-June 2005
19 SE Sensitivity with Scaling Process Node Application Soft Error Protection Required 180nm to 130nm Consumer None 90nm 65nm and below Networking and storage Military and aerospace Consumer Networking and storage Military and aerospace Consumer Networking and storage Memory Memory and logic Memory and logic Memory and logic Memory and logic Memory and logic Memory and logic Military and aerospace Memory and logic Source: iroc Technologies &
20 Existing Mitigation Techniques Layout level Reduction of sensitive area, using extra doping layer (epitaxial layer can help) or SOI etc. Circuit level Circuit techniques to reduce sensitivity to transients System level Space and time redundancy, Parity protection (only error detection), Error Correction Code (ECC), Error Detection and Correction Code (EDAC)
21 Circuit Level Mitigation V DD BLB WL R WL BL R T. M. Mnich, et. al., IEEE Trans. Nucl. Sci., p. 4620, 1983 Ootsuka et. al., IEDM 1998 Cypress Semiconductors P. Roche, et. al., IRPS 2004
22 System Level Mitigation Redundancy, majority voting Parity protection, EDAC/ECC
23 Design of SE Tolerant SRAMs SRAM in SoC: currently 50%; expected to reach ~90% by the end of the decade SE tolerance of SRAM will determine the system reliability Scaling and low power approaches for SRAMs are making SE immunity harder to achieve Circuit and system level hardening within areapower-performance constraints is essential motivation of my research
24 Summary Soft error causes silent data corruption the probability increases with technology scaling Both memory and logic circuits are susceptible Logic circuits have inherent masking mechanism Higher frequency makes them vulnerable Memories, e.g., SRAM is the most vulnerable Layout, circuit and system level mitigation techniques are used Mitigation techniques incur cost and degrade performance
25 Wait! It s not a Microsoft error It s just a soft error! THANK YOU
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