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1 Introduction to VLSI Design +1 (479)
2 Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal Fire by Riordan, Hoddeson 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
3 Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nmos and pmos MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 3
4 MOS Integrated Circuits 1970 s processors usually had only nmos transistors Inexpensive, but consume power while idle Intel bit SRAM Intel bit mproc 1980s-present: CMOS (Complementary MOS) processes for low idle power 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
5 Moore s Law Original (1965) Gordon Moore (Fairchild) The number of transistors on an IC would double every year. Revised (1975) Gordon Moore (Intel) A doubling every two years, rather than every year. Moore: "Cramming more components onto integrated circuits" Electronics, Vol. 38, No. 8, 1965 IEEE, IEDM Tech Digest (1975) 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
6 Moore s Law Moore's law suggests exponential growth (2x every 18 months) Is not about performance, not about chip size Hinted about the cost reduction Exponential transistor count Exponential complexity 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 6
7 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 7
8 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) Si Si - Si Si Si + Si Si + As Si Si B - Si Si Si Si Si Si Si 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 8
9 P-N Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 9
10 nmos Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate may not be made of metal Source Gate Drain Polysilicon SiO 2 n+ n+ p bulk Si 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 10
11 nmos Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 0 D 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 11
12 nmos Operation When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 1 D 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 12
13 pmos Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Polysilicon Source Gate Drain SiO 2 p+ p+ n bulk Si 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 13
14 CMOS Inverter A Y A Y V DD ON A=0 Y=1 OFF GND 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 14
15 CMOS NAND Gate A B Y A=1 OFF OFF Y=0 ON B=1 ON 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 15
16 CMOS NOR Gate A B Y A B Y 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 16
17 From Logic Symbol to Circuit Recall what you learned in CSCE2114 NAND Vdd IN1 IN2 OUT IN1 IN2 OUT IN1 IN2 OUT GND Logic Symbol Truth table Schematic 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 17
18 From Circuit to Layout Transistors are formed when poly is drawn over active/diffusion layer Vdd IN1 IN2 OUT IN1 IN2 OUT Contact Metal layer Poly layer Diffusion layer N-Well PMOS GND NMOS 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 18
19 Standard Cells Layout in out in1 in2 out VDD VDD n+ (n-implant) n-well p-well p-well n-well p+ (p-implant) contact poly (gate) in out in1 in2 metal 1 out cell bounrary p-well n-well p-well n-well GND GND INV NAND2 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 19
20 Standard Cells Layout Abstract The layout abstract hides details about standard cells and macros, leaves only interface geometries and connections Pins, obstacles, nets in out in1 in2 out VDD VDD metal 1 cell bounrary in out in1 out in2 GND INV GND NAND2 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 20
21 From Layout to Silicon Once the layout is done, it is send to foundries for fabrication Top-down view Side view 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 21
22 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process Video from Intel: 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 22
23 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line A Y GND V DD substrate tap nmos transistor pmos transistor well tap 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 23
24 Inverter Cross-Section Typically use p-type substrate for nmos transistors Requires n-well for body of pmos transistors A GND Y V DD SiO 2 n+ diffusion n+ n+ p+ p substrate n well p+ p+ diffusion polysilicon metal1 nmos transistor pmos transistor 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 24
25 Well and Substrate Contacts Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode) Use heavily doped well and substrate contacts / taps A GND Y V DD p+ n+ n+ p+ p+ n+ p substrate n well substrate tap well tap 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 25
26 Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal Metal 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 26
27 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2 p substrate 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 27
28 Oxidation Grow SiO 2 on top of Si wafer C with H 2 O or O 2 in oxidation furnace SiO 2 p substrate 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 28
29 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO 2 p substrate 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 29
30 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Top View Cross-section Photoresist SiO 2 p substrate 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 30
31 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO 2 p substrate 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 31
32 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranha etch (H 2 SO 4 + H 2 O 2 ) Necessary so resist doesn t melt in next step SiO 2 p substrate 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 32
33 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implantation Blast wafer with beam of As ions Ions blocked by SiO 2, only enter exposed Si SiO 2 n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 33
34 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 34
35 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor Polysilicon Thin gate oxide p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 35
36 Polysilicon Patterning Use same lithography process to pattern polysilicon Top View Polysilicon Cross-section Polysilicon Thin gate oxide p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 36
37 N-diffusion Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nmos source, drain, and n-well contact p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 37
38 N-diffusion (cont.) Pattern oxide and form n+ regions n+ Diffusion p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 38
39 N-diffusion (cont.) Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n+ p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 39
40 N-diffusion (cont.) Strip off oxide to complete patterning step n+ n+ n+ p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 40
41 P-Diffusion Similar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 41
42 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact p+ n+ n+ p+ p+ n+ Thick field oxide p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 42
43 Metalization Sputter on copper / aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal p+ n+ n+ p+ p+ n+ Metal Thick field oxide p substrate n well 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 43
44 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = minimum distance between source and drain Set by minimum width of polysilicon Feature size scales ~0.7x every 2 years both lateral and vertical Moore s law Normalize feature size when describing design rules Express rules in terms of λ= f/2 E.g. λ = 90 nm in 180 nm process 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 44
45 Design Rule Design rules ensure the layout is manufacturable. VDD 1 n-well 7 3 p-well 1: Min dist. (poly, contact) 2: Min dist. (metal 1) 3: Min dist. (active, well boundary) : Min width (poly) in out 5: Min width (metal 1) 6: Min dist. (contact) p-well n-well 7: Min dist. (contact, well bounrary) 6 GND 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 45
46 Types of Design Rules Size rules such as min/max width: The dimensions of any component (shape), e.g., length of a boundary edge or area of the shape, cannot be smaller than given min/max values. Separation rules such as min separation: Two shapes, either on the same layer or on adjacent layers, must be a minimum distance apart. Overlap rules such as min overlap: Two connected shapes on adjacent layers must have a certain amount of overlap due to inaccuracy of mask alignment to previously-made patterns on the wafer. Other rules Min/max area, min density etc 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 46
47 Types of Design Constraint Technology constraints Enable fabrication for a specific technology node and are derived from technology restrictions. Examples include minimum layout widths and spacing values between layout shapes. Electrical constraints Ensure the desired electrical behavior of the design. Examples include meeting maximum timing constraints for signal delay and staying below maximum coupling capacitances. Design methodology constraints Introduced to reduce the overall complexity of the design process. Examples include the use of preferred wiring directions during routing, and the placement of standard cells in rows. 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 47
48 VLSI Design Full-Custom Design Mostly used for microprocessor, memory and FPGAs Few design constraint: as long as it can be manufactured, it is allowed High performance, low power, small silicon area, and highly optimized High cost, time consuming, error-prone, and difficult to test Semi-Custom Design Uses standard cells and macro blocks as building materials Regularly place the cells in rows and arrays Need to add wires and vias for interconnection Standard flow exists with silicon-verified tools. Can be easily verified and tested. Short design cycle and time-to-market (Reduce cost) A slight degradation in performance and area (Increase cost) FPGA, PLA 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 48
49 VLSI Design Full-Custom Design Semi-Custom Design 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 49
50 Full-Custom Design (CPU) CPU Specification Comparison CPU Process Cores Transistor Count Die Size AMD Bulldozer 8C 32nm 8 1.2B 315mm 2 Intel Ivy Bridge 4C 22nm 4 1.4B 160mm 2 Intel Sandy Bridge E (6C) 32nm B 435mm 2 Intel Sandy Bridge 4C 32nm B 216mm 2 Intel Lynnfield 4C 45nm 4 774M 296mm 2 Intel Sandy Bridge 2C (GT2) 32nm 2 624M 149mm 2 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 50
51 Full-Custom Design (SRAM) SRAM cells are highly compact CMOS transistor arrays 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 51
52 Full-Custom Design (DRAM) DRAM unit cells are made of one NMOS and one capacitor Layout is highly vendor dependent 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 52
53 Standard-Cell-Based Design Macro Standard cells I/O cell 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 53
54 Custom vs. Synthesis 8-bit Implementations 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 54
55 FPGA Design In FPGA, logic elements and switch boxes as well as interconnect resources are pre-fabricated into the chip The logic elements and connections are programmable 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 55
56 Comparisons of Design Styles VLSI Design comparison FPGA provides fastest design time, with highest constraint on the cells and interconnects Semi-custom designs are extremely popular with application-specific integrated circuit (ASIC), allowing designing high performance chips with automated tools (Our focus) Full-Custom Standard-cell FPGA Cell size Variable Fixed height Fixed Cell type Variable Variable Programmable Cell placement Variable In row Fixed Interconnection Variable Variable Programmable Area Compact Compact to moderate Large Performance High High to moderate Low 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 56
57 Design Styles Tradeoffs 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 57
58 VLSI Semi-Custom Design Flow System Specification Architecture Design Logic/Circuit Design 64-bit Processor System Model RTL Netlist Freq Area Power 2GHz / 50mm 2 / 10W Synthesis Gate-level Netlist Physical Design Layout Verification Tape-out Fabrication Bare die Packaging & Testing Chip 9/5/2017 CSCE/ELEG 4914: Advnaced Digital Design 58
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