Low Power Radiation Tolerant CMOS Design using Commercial Fabrication Processes

Transcription

1 Low Power Radiation Tolerant CMOS Design using Commercial Fabrication Processes Amir Hasanbegovic Nanoelectronics Group, Dept. of Informatics, University of Oslo November 5, 2010

2 Overview Introduction Low power design, radiation environments and effects Methods Transistor structures, circuit- and architectural level hardening, layout considerations Design Flow for radiation tolerant ASICs Summary

3 Introduction Low power design techniques Multiple supply voltages MTCMOS Multiple threshold voltage CMOS. Level shifters Subthreshold to above threshold voltage level shifting Radiation hardened by design (RHBD) Methodologies Circuit level hardening Architectural level hardening Layout considerations => Low power, radiation tolerant circuits

4 Introduction Radiation environments Trapped radiation belts Protons, electrons Galactic cosmic rays High energy particles Solar flares Terrestrial radiation Cosmic ray induced neutrons Radiation effects (soft/hard errors) Single event transients (SET) Single event upsets (SEU) Multiple bit upsets (MBU) Single event latchup (SEL) Total ionizing dose effects (TID) Particle induced charge collection causing voltage fluctuations in circuit nodes

5 Introduction Why VHDL synthesis on ASICs for radiation tolerance applications? Motivations TID induced leakage currents and Vth shifts in new tech. nodes. Power consumption Design flexibility on ASICs. Speed Radhard by process technology lag (2-3 generations) Challenges Critical charge, Qcrit the amount of charge required to upset a capacitive node in a circuit Increased design density

6 Transistor -Structures and -Properties in RHBD Applications TID induced leakage currents in standard transistors Inter device leakage Intra device leakage Annular layout transistors STI sidewalls do not exist between source and drain in the annular structure => less leakage currents May be relevant for low voltage operation ION/IOFF ratio

7 Architectural level hardening Triple modular redundancy (TMR) Temporal Sampling Majority voters Dual modular redundancy (DMR) Dual interlocked cell (DICE) Guard gates (C-elements) Interlocked combinational logic

8 Circuit level hardening Dual data inputs Dual clock A=C, B=D SEU immune DICE latch A SET event on any single node in a DICE configuration is not able to trigger the feedback due to the fast recovery time imposed by the interlocked node pairs. C-elements

9 SET and SEU tolerant layout technique Layout considerations for radiation tolerance Angle of particle impact Interleaving of critical nodes Inter device leakage Guard bands Spatial distribution

10 Design Flow for radiation tolerant ASICs Synopsys Sentaurus TCAD Low level transistor-/structure characterization SET, SEU, MBU, TID induced leakage, ++ Cadence Virtuoso schematic Cell simulations Charge injection simulations/scripts Cell characterization Cadence Virtuoso layout Post layout simulations Cell characterization VHDL synthesis VHDL model Post synthesis analysis Static timing analysis Cadence SoC Encounter RTL Compiler Floorplan/ powerplanning Macro-/Standard cell placement Timing analysis and refinement AMS 0.35 um, TSMC 90 nm, STM 65 nm GDSII 45 nm available in 2011 (?) A SOI process is under consideration

11 Setup for radiation testing -Soft error detection using a Spartan 3 development board - VHDL, MATLAB

12 Summary Design of digital circuits Robust low power, radiation tolerant Radiation tolerant standard cells including level shifters Soft error characterization setup Possibility for On-chip MEMS/RF MEMS ( CMOS MEMS ) Mixed-signal circuits

13 Summary Thank you for your attention Questions?