on-chip Design for LAr Front-end Readout

Size: px
Start display at page:

Download "on-chip Design for LAr Front-end Readout"

Transcription

1 Silicon-on on-sapphire (SOS) Technology and the Link-on on-chip Design for LAr Front-end Readout Ping Gui, Jingbo Ye, Ryszard Stroynowski Department of Electrical Engineering Physics Department Southern Methodist University ATLAS Liquid Argon Colorimeter Upgrade Workshop June 23,

2 Outline Introduction Silicon-on on-sapphire (SoS( SoS) Technology SoS Test Chip Link-on on-chip Design 2

3 Radiation-hardening hardening-by-design (RHBD) The wide availability of commercial IC processes has led to the philosophy of radiation hardening by design. Explore circuit topologies and layout techniques to create radiation-tolerant circuits Submicron bulk CMOS inexpensive BiCMOS ideal for mixed-signal design, but very expensive SOI/SOS relatively new, growing in popularity 3

4 Radiation Hardening by Design Total Dose Effect Enclosed layout Transistors Guarded ring Single Event Effect Marjory vote circuits Error detection/correction Coding Charge dissipation technique Temporal filtering technique G. Anelli, 2000 IEEE Nuclear Science Symposium and Medical Imaging Conference Trade-off between radiation tolerance, performance, area and power dissipation. 4

5 Radiation-hard design challenges Techniques that minimize one radiation mechanism may have little or no effect on another. Years ago, total dose concerns dominated radiation tolerant design, but they are now secondary to single event effects (SEEs). SEEs have grown in importance as feature sizes, capacitances, and operating voltages have been reduced. 5

6 IC Feature Size and Radiation Effects Tim Holman, Radiation Effects on Microelectronics Short Course

7 Peregrine s s SOS Technology SOS Process s i o 2 BULK CMOS P channel FET N channel FET Insulating sapphire substrate 100 nm 200 μm Peregrine s SOS industry s first and only commercially qualified SOS technology No Single-event Latch-up in SoS CMOS! Increased immunity to SEE Ideal for radiationtolerant mixed-signal circuit design due to minimum substrate noise 7

8 Process Features Minimum substrate noise Higher level integration of RF, mixed-signal and digital circuitry. Reduced Parasitic capacitance High performance Low Power consumption Minimum crosstalk Widely used in RF and space products Transparent substrate allows for compact and simple integration with optical devices 8

9 Flipped OE devices on SoS substrate UTSi integrated photo detector VCSEL driver circuitry UTSi integrated circuitry receiver circuitry flip chip attachment quad VCSEL array quad PIN array transparent sapphire substrate (UTSi) MMF ribbon fiber 200 um active CMOS layer Flip-chip bonding of OE devices to CMOS on sapphire No wire-bonds package performance scales to higher data rates Rugged and compact package 9

10 Peregrine Space Optical Transceiver MTP Connector Module 0.5-um SoS Single 4+4 transceiver component with variable data rates (CML interface) Minimum data rate 10 Mbps Maximum data rate 2.7 Gbps per channel Radiation Total Ionizing Dose: 100 krad(si) SEU: > 20 MeV-cm2/mg 15 year operational lifetime 15 mm height Berg MegArray PCB socket 125 mw per channel power consumption (dissipated to panel mount) Vibration grms for 3 minutes total 10

11 SoS CMOS v.s.. Bulk CMOS 0.25 μm SoS 0.13 μm m Bulk CMOS Performance Leakage Current Power Dissipation Crosstalk Cost Up to 10 GHz Substrate as an insulator (10 14 ohm/m at room temperature). Reduced substrate junction capacitance leads to lower leakage current. Reduced parasitic capacitance also leads to a lower power dissipation Minimum crosstalk due to reduced substrate capacitance $100k for wafer mask set; $1000 per wafer Up to 10 GHz High Leakage current Substrate noise causes crosstalk between channels $800k for wafer mask set; $800 per wafer 11

12 Back-channel channel Leakage Current in SOS Possible Leakage path along the Si/Sapphire interface 12

13 Preliminary Radiation Test Results on 0.5-µm SoS CMOS Technology 2.5Gbps Before radiation Transceiver chip made in 0.5um SoS CMOS Technology 2.5Gbps Post-rad 100Mrad 1.6 Gbps Post-rad 100Mrad Radiation test setup at the Northeast Proton Therapy Center 13

14 Dedicated Radiation Test Chip for a 0.25-µm m SOS CMOS Single NMOS and PMOS Current mirrors/ resistors Ring oscillators, Ring oscillators Shift registers Shift registers Individual Standard Cells Transistor XY matrix Ring Oscillators to characterize the performance and power dissipation Shift registers to characterize SEE Standard layout, edgeless layout, majority vote circuit, resistively hardened cells Digital Standard cells Current mirrors Resistors 14

15 Transistor Test Structures NMOS and PMOS Array PMOS and NMOS with different size Different lengths to characterize back-channel channel leakage current Each transistor implemented in four layouts Standard, edgeless (ELT), two-finger and four-finger finger layout to characterize edge leakage current Edgeless (ELT) 10 One-finger 5 Two-finger 15

16 SOS Rad-hard Test Chip Layout Majority vote circuitry CMOS Ring Oscillators Differential Ring Oscillator Shift Registers Individual gates Resistors Transistors array PLL cells Chip was submitted for fabrication in Oct

17 Link-on on-chip Architecture REFclock PLL and clock generator Flip-chip bonding Parallel Data encoder TX transmitter Module Receiver Module Parallel Data Photonic Deserializer Decoder serializer Laser Driver TIA/LA Flip-chip bonding Laser PIN Optical data REFclock Clock/Data recovery Improve performance No off-chip high speed lines Flip-chip bonding reduces capacitance and inductance Reduce power consumption No 50-Ohm transmission lines between chips 17

18 2.5-Gbps Serializer Architecture 5 bit SR1 (1,5,9,13,17) Bits 1,3,5,7,9, 11,13,15,17,19 20bit 20-bit Word Latch 5 bit 5 bit SR2 SR3 (3,7,11,15,19) Latch (2,6,10,14,18) Mux1 Mux3 Serial output Ref_clk 5 bit SR4 (4,8,12,16,20) Latch Mux2 Latch Shift registers Bits 2,4,6,8,10, 12,14,16,18,20 Word clock (125MHz) Load clk (125MHz) PLL & Clk generator Half bit clk (625MHz) Bit clk (1.25GHz) 18

19 PLL and Clock Generator 19

20 Phase-Locked Loop Self-biasing structure [1] Remove process technology and environmental variability, low input tracking jitter, Wide operating frequency range Phase-frequency detector with equal short duration output pulses for in- phase inputs Charge-pump with symmetric load VCO with differential buffer delay stage with symmetric loads Loop filter [1] J. G. Maneatis, low-jitter Process-Independent DLL and PLL Based on Self- Biased Techniques, IEEE JSCC, Vol. 31, No. 11, Nov

21 PLL Layout gnd vdd PFD S2D Charge Pump1 Charge Pump2 Vcntrl1 Vcntrl2 d i v 5 start up div4 D2S VCO Bias Gen 21

22 Serializer Layout 22

23 Serializer + PLL & Clock Generator Serializer Clk generator PLL 23

24 1.25GHz PLL Simulation Results Lock time=1.5us 24

25 Clock Generator 1.25GHz 25

26 Serializer Simulation at 2.5-Gbps 26

27 Clock generator 1.6GHz 27

28 Serializer 3.2Gpbs 28

29 Conclusion Dedicated test Chip lab has been tested and fabricated Lab and radiation testing is in progress Link-on on-chip serializer and PLL & clock generator components are completed. 29

30 Acknowledgement Paulo Moreira at CERN-EP/MIC EP/MIC for sharing GOL link design and many useful discussions Peregrine for sharing the cost of the chip fabrication Thank You! 30

Southern Methodist University Dallas, TX, Southern Methodist University Dallas, TX, 75275

Southern Methodist University Dallas, TX, Southern Methodist University Dallas, TX, 75275 Single Event Effects in a 0.25 µm Silicon-On-Sapphire CMOS Technology Wickham Chen 1, Tiankuan Liu 2, Ping Gui 1, Annie C. Xiang 2, Cheng-AnYang 2, Junheng Zhang 1, Peiqing Zhu 1, Jingbo Ye 2, and Ryszard

More information

Southern Methodist University Dallas, TX, Department of Physics. Southern Methodist University Dallas, TX, 75275

Southern Methodist University Dallas, TX, Department of Physics. Southern Methodist University Dallas, TX, 75275 Total Ionization Dose Effect Studies of a 0.25 µm Silicon-On-Sapphire CMOS Technology Tiankuan Liu 2, Ping Gui 1, Wickham Chen 1, Jingbo Ye 2, Cheng-AnYang 2, Junheng Zhang 1, Peiqing Zhu 1, Annie C. Xiang

More information

10 Gb/s Radiation-Hard VCSEL Array Driver

10 Gb/s Radiation-Hard VCSEL Array Driver 10 Gb/s Radiation-Hard VCSEL Array Driver K.K. Gan 1, H.P. Kagan, R.D. Kass, J.R. Moore, D.S. Smith Department of Physics The Ohio State University Columbus, OH 43210, USA E-mail: gan@mps.ohio-state.edu

More information

Total Ionization Dose Effects and Single-Event Effects Studies Of a 0.25 μm Silicon-On-Sapphire CMOS Technology

Total Ionization Dose Effects and Single-Event Effects Studies Of a 0.25 μm Silicon-On-Sapphire CMOS Technology > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Total Ionization Dose Effects and Single-Event Effects Studies Of a 0.25 μm Silicon-On-Sapphire CMOS Technology

More information

The Design of a High Speed Low Power Phase Locked Loop

The Design of a High Speed Low Power Phase Locked Loop The Design of a High Speed Low Power Phase Locked Loop Tiankuan Liu a, Datao Gong a, Suen Hou b, Zhihua Liang a, Chonghan Liu a, Da-Shung Su b, Ping-Kun Teng b, Annie C. Xiang a, Jingbo Ye a a CERN of

More information

Radiation-hard/high-speed data transmission using optical links

Radiation-hard/high-speed data transmission using optical links Radiation-hard/high-speed data transmission using optical links K.K. Gan a, B. Abi c, W. Fernando a, H.P. Kagan a, R.D. Kass a, M.R.M. Lebbai b, J.R. Moore a, F. Rizatdinova c, P.L. Skubic b, D.S. Smith

More information

Development of Radiation-Hard ASICs for the ATLAS Phase-1 Liquid Argon Calorimeter Readout Electronics Upgrade

Development of Radiation-Hard ASICs for the ATLAS Phase-1 Liquid Argon Calorimeter Readout Electronics Upgrade Development of Radiation-Hard ASICs for the ATLAS Phase-1 Liquid Argon Calorimeter Readout Electronics Upgrade Tim Andeen*, Jaroslav BAN, Nancy BISHOP, Gustaaf BROOIJMANS, Alex EMERMAN,Ines OCHOA, John

More information

A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver

A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver Ö. Çobanoǧlu a, P. Moreira a, F. Faccio a a CERN, PH-ESE-ME, 1211 Geneva 23, Switzerland Abstract ozgur.cobanoglu@cern.ch This paper

More information

A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR

A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR Yang-Shyung Shyu * and Jiin-Chuan Wu Dept. of Electronics Engineering, National Chiao-Tung University 1001 Ta-Hsueh Road, Hsin-Chu, 300, Taiwan * E-mail:

More information

A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade Available online at www.sciencedirect.com Physics Procedia 37 (2012 ) 1618 1629 TIPP 2011 - Technology and Instrumentation in Particle Physics 2011 A high speed serializer ASIC for ATLAS Liquid Argon calorimeter

More information

QPLL a Quartz Crystal Based PLL for Jitter Filtering Applications in LHC

QPLL a Quartz Crystal Based PLL for Jitter Filtering Applications in LHC QPLL a Quartz Crystal Based PLL for Jitter Filtering Applications in LHC Paulo Moreira and Alessandro Marchioro CERN-EP/MIC, Geneva Switzerland 9th Workshop on Electronics for LHC Experiments 29 September

More information

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1 Contents 1 FUNDAMENTAL CONCEPTS 1 1.1 What is Noise Coupling 1 1.2 Resistance 3 1.2.1 Resistivity and Resistance 3 1.2.2 Wire Resistance 4 1.2.3 Sheet Resistance 5 1.2.4 Skin Effect 6 1.2.5 Resistance

More information

Ping Gui, Member, IEEE, Peiqing Zhu, Wickham Chen, Student Member, IEEE, Dennis Wu, Sungyong Jung, Senior Member, IEEE

Ping Gui, Member, IEEE, Peiqing Zhu, Wickham Chen, Student Member, IEEE, Dennis Wu, Sungyong Jung, Senior Member, IEEE > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 A TID Tolerant, Wide Band and Low Jitter Phase-Locked Loop in 0.25 m CMOS Silicon-on-Sapphire Technology Ping Gui,

More information

A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique

A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.3, JUNE, 2014 http://dx.doi.org/10.5573/jsts.2014.14.3.331 A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique

More information

Signal Integrity Design of TSV-Based 3D IC

Signal Integrity Design of TSV-Based 3D IC Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues

More information

The GBTIA, a 5 Gbit/s Radiation-Hard Optical Receiver for the SLHC Upgrades

The GBTIA, a 5 Gbit/s Radiation-Hard Optical Receiver for the SLHC Upgrades The GBTIA, a 5 Gbit/s Radiation-Hard Optical Receiver for the SLHC Upgrades M. Menouni a, P. Gui b, P. Moreira c a CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France b SMU, Southern Methodist

More information

High-Speed/Radiation-Hard Optical Links

High-Speed/Radiation-Hard Optical Links High-Speed/Radiation-Hard Optical Links K.K. Gan, H. Kagan, R. Kass, J. Moore, D.S. Smith The Ohio State University P. Buchholz, S. Heidbrink, M. Vogt, M. Ziolkowski Universität Siegen September 8, 2016

More information

Dedication. To Mum and Dad

Dedication. To Mum and Dad Dedication To Mum and Dad Acknowledgment Table of Contents List of Tables List of Figures A B A B 0 1 B A List of Abbreviations Abstract Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative

More information

Development of a Radiation Tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments.

Development of a Radiation Tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments. Development of a Radiation Tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments. K. Kloukinas, F. Faccio, A. Marchioro, P. Moreira, CERN/EP-MIC,

More information

OPTICAL LINK OF THE ATLAS PIXEL DETECTOR

OPTICAL LINK OF THE ATLAS PIXEL DETECTOR OPTICAL LINK OF THE ATLAS PIXEL DETECTOR K.K. Gan, W. Fernando, P.D. Jackson, M. Johnson, H. Kagan, A. Rahimi, R. Kass, S. Smith Department of Physics, The Ohio State University, Columbus, OH 43210, USA

More information

High Voltage Operational Amplifiers in SOI Technology

High Voltage Operational Amplifiers in SOI Technology High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper

More information

Radiation-hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector

Radiation-hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector Radiation-hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector P. D. Jackson 1, K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, A. Rahimi, C. Rush, S. Smith, R. Ter-Antonian, M.M. Zoeller Department

More information

A Radiation Tolerant Laser Driver Array for Optical Transmission in the LHC Experiments

A Radiation Tolerant Laser Driver Array for Optical Transmission in the LHC Experiments A Radiation Tolerant Laser Driver Array for Optical Transmission in the LHC Experiments Giovanni Cervelli, Alessandro Marchioro, Paulo Moreira, and Francois Vasey CERN, EP Division, 111 Geneva 3, Switzerland

More information

A 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization. Hegang Hou*, Zongmin Wang, Ying Kong, Xinmang Peng, Haitao Guan, Jinhao Wang, Yan Ren

A 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization. Hegang Hou*, Zongmin Wang, Ying Kong, Xinmang Peng, Haitao Guan, Jinhao Wang, Yan Ren Joint International Mechanical, Electronic and Information Technology Conference (JIMET 2015) A 14-bit 2.5 GS/s based on Multi-Clock Synchronization Hegang Hou*, Zongmin Wang, Ying Kong, Xinmang Peng,

More information

LSI and Circuit Technologies for the SX-8 Supercomputer

LSI and Circuit Technologies for the SX-8 Supercomputer LSI and Circuit Technologies for the SX-8 Supercomputer By Jun INASAKA,* Toshio TANAHASHI,* Hideaki KOBAYASHI,* Toshihiro KATOH,* Mikihiro KAJITA* and Naoya NAKAYAMA This paper describes the LSI and circuit

More information

Self-Biased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas

Self-Biased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Self-Biased PLL/DLL ECG721 60-minute Final Project Presentation Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Outline Motivation Self-Biasing Technique Differential Buffer

More information

A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology

A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology Journal of Instrumentation OPEN ACCESS A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology To cite this article: G Mazza et al View the article online for updates and enhancements. Related

More information

A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems

A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems M. Meghelli 1, A. Rylyakov 1, S. J. Zier 2, M. Sorna 2, D. Friedman 1 1 IBM T. J. Watson Research Center 2 IBM

More information

ISSCC 2006 / SESSION 13 / OPTICAL COMMUNICATION / 13.2

ISSCC 2006 / SESSION 13 / OPTICAL COMMUNICATION / 13.2 13.2 An MLSE Receiver for Electronic-Dispersion Compensation of OC-192 Fiber Links Hyeon-min Bae 1, Jonathan Ashbrook 1, Jinki Park 1, Naresh Shanbhag 2, Andrew Singer 2, Sanjiv Chopra 1 1 Intersymbol

More information

THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL

THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL IN CMOS TECHNOLOGY L. Majer, M. Tomáška,V. Stopjaková, V. Nagy, and P. Malošek Department of Microelectronics, Slovak Technical University, Ilkovičova 3, Bratislava,

More information

Self Biased PLL/DLL. ECG 721 Memory Circuit Design (Spring 2017) Dane Gentry 4/17/17

Self Biased PLL/DLL. ECG 721 Memory Circuit Design (Spring 2017) Dane Gentry 4/17/17 Self Biased PLL/DLL ECG 721 Memory Circuit Design (Spring 2017) Dane Gentry 4/17/17 1 Jitter Self Biased PLL/DLL Differential Buffer Delay Fig. 19.57 Bias Generator Self Biased DLL Input/Output p Delay

More information

AMICSA Bridging Science & Applications F r o m E a r t h t o S p a c e a n d b a c k. Kayser-Threde GmbH. Space

AMICSA Bridging Science & Applications F r o m E a r t h t o S p a c e a n d b a c k. Kayser-Threde GmbH. Space Bridging Science & Applications F r o m E a r t h t o S p a c e a n d b a c k E a r t h S p a c e & F u t u r e Kayser-Threde GmbH Space Industrial Applications AMICSA 2008 First radiation test results

More information

A Low-Power, Radiation-Hard Gigabit Serializer for use in the CMS Electromagnetic Calorimeter

A Low-Power, Radiation-Hard Gigabit Serializer for use in the CMS Electromagnetic Calorimeter IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 47, NO. 1, FEBRUARY 2000 13 A Low-Power, Radiation-Hard Gigabit Serializer for use in the CMS Electromagnetic Calorimeter P. Denes, S. Baier, Member, IEEE, J.-M.

More information

Non Hermetic Fiber Optic Transceivers for Space Applications. Chuck Tabbert VP of Sales & Marketing inc.

Non Hermetic Fiber Optic Transceivers for Space Applications. Chuck Tabbert VP of Sales & Marketing inc. Non Hermetic Fiber Optic Transceivers for Space Applications Chuck Tabbert VP of Sales & Marketing ctabbert@ultracomm inc.com (505) 823 1293 1 Agenda Motivation X80 QM Space Product Overview Space Qualification

More information

Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology

Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology 2009 IEEE Nuclear Science Symposium, Orlando, Florida, October 28 th 2009 Jean-Francois Genat On behalf of Mircea Bogdan 1, Henry J. Frisch

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements

More information

Research on Self-biased PLL Technique for High Speed SERDES Chips

Research on Self-biased PLL Technique for High Speed SERDES Chips 3rd International Conference on Machinery, Materials and Information Technology Applications (ICMMITA 2015) Research on Self-biased PLL Technique for High Speed SERDES Chips Meidong Lin a, Zhiping Wen

More information

Extreme Temperature Invariant Circuitry Through Adaptive DC Body Biasing

Extreme Temperature Invariant Circuitry Through Adaptive DC Body Biasing Extreme Temperature Invariant Circuitry Through Adaptive DC Body Biasing W. S. Pitts, V. S. Devasthali, J. Damiano, and P. D. Franzon North Carolina State University Raleigh, NC USA 7615 Email: wspitts@ncsu.edu,

More information

UT90nHBD Hardened-by-Design (HBD) Standard Cell Data Sheet February

UT90nHBD Hardened-by-Design (HBD) Standard Cell Data Sheet February Semicustom Products UT90nHBD Hardened-by-Design (HBD) Standard Cell Data Sheet February 2018 www.cobham.com/hirel The most important thing we build is trust FEATURES Up to 50,000,000 2-input NAND equivalent

More information

Voltage Controlled Quartz Crystal Oscillator (VCXO) ASIC

Voltage Controlled Quartz Crystal Oscillator (VCXO) ASIC General: Voltage Controlled Quartz Oscillator (VCXO) ASIC Paulo Moreira CERN, 21/02/2003 The VCXO ASIC is a test structure designed by the CERN microelectronics group in a commercial 0.25 µm CMOS technology

More information

Phase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li

Phase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li 5th International Conference on Computer Sciences and Automation Engineering (ICCSAE 2015) Phase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li

More information

Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters

Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters International Journal of Electronics and Electrical Engineering Vol. 2, No. 4, December, 2014 Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters Jefferson A. Hora, Vincent Alan Heramiz,

More information

A 3-10GHz Ultra-Wideband Pulser

A 3-10GHz Ultra-Wideband Pulser A 3-10GHz Ultra-Wideband Pulser Jan M. Rabaey Simone Gambini Davide Guermandi Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-136 http://www.eecs.berkeley.edu/pubs/techrpts/2006/eecs-2006-136.html

More information

A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector

A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.287 ISSN(Online) 2233-4866 A 10-Gb/s Multiphase Clock and Data Recovery

More information

A rad-hard 8-channel 12-bit resolution ADC for slow control applications in the LHC environment

A rad-hard 8-channel 12-bit resolution ADC for slow control applications in the LHC environment A rad-hard 8-channel 12-bit resolution ADC for slow control applications in the LHC environment G. Magazzù 1,A.Marchioro 2,P.Moreira 2 1 INFN-PISA, Via Livornese 1291 56018 S.Piero a Grado (Pisa), Italy

More information

A 4 Channel Waveform Sampling ASIC in 130 nm CMOS

A 4 Channel Waveform Sampling ASIC in 130 nm CMOS A 4 Channel Waveform Sampling ASIC in 130 nm CMOS E. Oberla, H. Grabas, J.F. Genat, H. Frisch Enrico Fermi Institute, University of Chicago K. Nishimura, G. Varner University of Hawai I Large Area Picosecond

More information

ATLAS Pixel Opto-Electronics

ATLAS Pixel Opto-Electronics ATLAS Pixel Opto-Electronics K.E. Arms, K.K. Gan, P. Jackson, M. Johnson, H. Kagan, R. Kass, A.M. Rahimi, C. Rush, S. Smith, R. Ter-Antonian, M.M. Zoeller Department of Physics, The Ohio State University,

More information

Optimization of Digitally Controlled Oscillator with Low Power

Optimization of Digitally Controlled Oscillator with Low Power IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled

More information

ECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment

ECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment 1 ECEN 720 High-Speed Links: Circuits and Systems Lab3 Transmitter Circuits Objective To learn fundamentals of transmitter and receiver circuits. Introduction Transmitters are used to pass data stream

More information

160-Gb/s Bidirectional Parallel Optical Transceiver Module for Board-Level Interconnects

160-Gb/s Bidirectional Parallel Optical Transceiver Module for Board-Level Interconnects 160-Gb/s Bidirectional Parallel Optical Transceiver Module for Board-Level Interconnects Fuad Doany, Clint Schow, Jeff Kash C. Baks, D. Kuchta, L. Schares, & R. John IBM T. J. Watson Research Center doany@us.ibm.com

More information

A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface

A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 225 A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit

More information

A 1.5 Gbps Transceiver Chipset in 0.13-mm CMOS for Serial Digital Interface

A 1.5 Gbps Transceiver Chipset in 0.13-mm CMOS for Serial Digital Interface JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.4, AUGUST, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2017.17.4.552 ISSN(Online) 2233-4866 A 1.5 Gbps Transceiver Chipset in 0.13-mm

More information

/$ IEEE

/$ IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for

More information

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 Dummy Gate-Assisted n-mosfet Layout for a Radiation-Tolerant Integrated Circuit Min Su Lee and Hee Chul Lee Abstract A dummy gate-assisted

More information

EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Announcements

EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Announcements EE290C - Spring 04 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 11 Components Phase-Locked Loops Viterbi Decoder Borivoje Nikolic March 2, 04. Announcements Homework #2 due

More information

Comparison And Performance Analysis Of Phase Frequency Detector With Charge Pump And Voltage Controlled Oscillator For PLL In 180nm Technology

Comparison And Performance Analysis Of Phase Frequency Detector With Charge Pump And Voltage Controlled Oscillator For PLL In 180nm Technology IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 4, Ver. I (Jul - Aug. 2015), PP 22-30 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Comparison And Performance Analysis

More information

High-speed Serial Interface

High-speed Serial Interface High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications

More information

An Analog Phase-Locked Loop

An Analog Phase-Locked Loop 1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential

More information

DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS

DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,

More information

CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL

CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL IEEE INDICON 2015 1570186537 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 60 61 62 63

More information

Sudatta Mohanty, Madhusmita Panda, Dr Ashis kumar Mal

Sudatta Mohanty, Madhusmita Panda, Dr Ashis kumar Mal International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May-2014 45 Design and Performance Analysis of a Phase Locked Loop using Differential Voltage Controlled Oscillator Sudatta

More information

SiNANO-NEREID Workshop:

SiNANO-NEREID Workshop: SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates

More information

Towards an ADC for the Liquid Argon Electronics Upgrade

Towards an ADC for the Liquid Argon Electronics Upgrade 1 Towards an ADC for the Liquid Argon Electronics Upgrade Gustaaf Brooijmans Upgrade Workshop, November 10, 2009 2 Current LAr FEB Existing FEB (radiation tolerant for LHC, but slhc?) Limits L1 latency

More information

320MHz Digital Phase Lock Loop. Patrick Spinney Department of Electrical Engineering University of Maine

320MHz Digital Phase Lock Loop. Patrick Spinney Department of Electrical Engineering University of Maine 320MHz Digital Phase Lock Loop Patrick Spinney Department of Electrical Engineering University of Maine December 2004 Abstract DPLLs (Digital Phase Locked Loop) are commonly used in communications systems.

More information

EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS

EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS P. MARTIN-GONTHIER, F. CORBIERE, N. HUGER, M. ESTRIBEAU, C. ENGEL,

More information

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore

More information

A CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati 1 B.K.Arun Teja 2 K.Sai Ravi Teja 3

A CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati 1 B.K.Arun Teja 2 K.Sai Ravi Teja 3 IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 06, 2015 ISSN (online): 2321-0613 A CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati

More information

An Asymmetrical Bulk CMOS Switch for 2.4 GHz Application

An Asymmetrical Bulk CMOS Switch for 2.4 GHz Application Progress In Electromagnetics Research Letters, Vol. 66, 99 104, 2017 An Asymmetrical Bulk CMOS Switch for 2.4 GHz Application Lang Chen 1, * and Ye-Bing Gan 1, 2 Abstract A novel asymmetrical single-pole

More information

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c,

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c, 4th International Conference on Computer, Mechatronics, Control and Electronic Engineering (ICCMCEE 2015) A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a,

More information

MHz phase-locked loop

MHz phase-locked loop SPECIFICATION 1 FEATURES 50 800 MHz phase-locked loop TSMC CMOS 65 nm Output frequency from 50 to 800 MHz Reference frequency from 4 to 30 MHz Power supply 1.2 V CMOS output Supported foundries: TSMC,

More information

LETTER A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

LETTER A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation 196 LETTER A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation Ching-Yuan YANG a), Member and Jung-Mao LIN, Nonmember SUMMARY In this letter, a 1.25-Gb/s 0.18-µm

More information

The 20th Microelectronics Workshop Development status of SOI ASIC / FPGA

The 20th Microelectronics Workshop Development status of SOI ASIC / FPGA The 20th Microelectronics Workshop Development status of SOI ASIC / FPGA Oct. 30th 2007 Electronic, Mechanical Components and Materials Engineering Group, JAXA H.Shindou Background In 2003, critical EEE

More information

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter University of Pennsylvania ScholarlyCommons epartmental Papers (ESE) epartment of Electrical & Systems Engineering 7-1-2003 A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and

More information

A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC

A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC M. Åberg 2, A. Rantala 2, V. Hakkarainen 1, M. Aho 1, J. Riikonen 1, D. Gomes Martin 2, K. Halonen 1 1 Electronic Circuit Design Laboratory Helsinki University

More information

Ultra-Low-Power Phase-Locked Loop Design

Ultra-Low-Power Phase-Locked Loop Design Design for MOSIS Educational Program (Research) Ultra-Low-Power Phase-Locked Loop Design Prepared by: M. Shahriar Jahan, Xiaojun Tu, Tan Yang, Junjie Lu, Ashraf Islam, Kai Zhu, Song Yuan, Chandradevi Ulaganathan,

More information

Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition

Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition P. K. Rout, B. P. Panda, D. P. Acharya and G. Panda 1 Department of Electronics and Communication Engineering, School of Electrical

More information

A 4-Channel Fast Waveform Sampling ASIC in 130 nm CMOS

A 4-Channel Fast Waveform Sampling ASIC in 130 nm CMOS A 4-Channel Fast Waveform Sampling ASIC in 130 nm CMOS E. Oberla, H. Grabas, M. Bogdan, J.F. Genat, H. Frisch Enrico Fermi Institute, University of Chicago K. Nishimura, G. Varner University of Hawai I

More information

Higher School of Economics, Moscow, Russia. Zelenograd, Moscow, Russia

Higher School of Economics, Moscow, Russia. Zelenograd, Moscow, Russia Advanced Materials Research Online: 2013-07-31 ISSN: 1662-8985, Vols. 718-720, pp 750-755 doi:10.4028/www.scientific.net/amr.718-720.750 2013 Trans Tech Publications, Switzerland Hardware-Software Subsystem

More information

LSI ON GLASS SUBSTRATES

LSI ON GLASS SUBSTRATES LSI ON GLASS SUBSTRATES OUTLINE Introduction: Why System on Glass? MOSFET Technology Low-Temperature Poly-Si TFT Technology System-on-Glass Technology Issues Conclusion System on Glass CPU SRAM DRAM EEPROM

More information

Efficient Optical Communications Using Multi-Bit Differential Signaling

Efficient Optical Communications Using Multi-Bit Differential Signaling Efficient Optical Communications Using Multi-Bit Differential Signaling Donald M. Chiarulli 1, Steven P. Levitan 2, Samuel J. Dickerson 2, Jason D. Bakos 3, Joel Martin 2 1 Department of Computer Science,

More information

A Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell

A Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell A Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell Devi Singh Baghel 1, R.C. Gurjar 2 M.Tech Student, Department of Electronics and Instrumentation, Shri G.S. Institute of

More information

A SiGe 6 Modulus Prescaler for a 60 GHz Frequency Synthesizer

A SiGe 6 Modulus Prescaler for a 60 GHz Frequency Synthesizer A SiGe 6 Modulus Prescaler for a 6 GHz Frequency Synthesizer Noorfazila Kamal,YingboZhu, Said F. Al-Sarawi, Neil H.E. Weste,, and Derek Abbott The School of Electrical & Electronic Engineering, University

More information

A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker

A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker Robert P. Johnson Pavel Poplevin Hartmut Sadrozinski Ned Spencer Santa Cruz Institute for Particle Physics The GLAST Project

More information

Hot Topics and Cool Ideas in Scaled CMOS Analog Design

Hot Topics and Cool Ideas in Scaled CMOS Analog Design Engineering Insights 2006 Hot Topics and Cool Ideas in Scaled CMOS Analog Design C. Patrick Yue ECE, UCSB October 27, 2006 Slide 1 Our Research Focus High-speed analog and RF circuits Device modeling,

More information

Lecture 23: PLLs. Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class

Lecture 23: PLLs. Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 23: PLLs Announcements Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class Open book open notes Project

More information

Inductor based switching DC-DC converter for low voltage power distribution in SLHC

Inductor based switching DC-DC converter for low voltage power distribution in SLHC Inductor based switching DC-DC converter for low voltage power distribution in SLHC S. Michelis a,b, F. Faccio a, A. Marchioro a, M. Kayal b, a CERN, 1211 Geneva 23, Switzerland b EPFL, 115 Lausanne, Switzerland

More information

A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications

A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa Tokyo Institute

More information

An SOI-based High-Voltage, High-Temperature Gate-Driver for SiC FET

An SOI-based High-Voltage, High-Temperature Gate-Driver for SiC FET An SOI-based High-Voltage, High-Temperature Gate-Driver for SiC FET M. A Huque 1, R. Vijayaraghavan 1, M. Zhang 1, B. J. Blalock 1, L M. Tolbert 1,2, and S. K. Islam 1 1 Department of Electrical and Computer

More information

PE29102 Document Category: Product Specification

PE29102 Document Category: Product Specification Document Category: Product Specification UltraCMOS, 40 MHz Features High- and Low-side FET drivers Dead-time control Fast propagation delay, 9 ns Tri-state enable mode Sub-nanosecond rise and fall time

More information

SPACE-QUALIFIED 1.25GB/S NANO-TECHNOLOGICAL TRANSPONDER FOR SPACE WIRE OPTICAL/ELECTRICAL INTERCONNECTS

SPACE-QUALIFIED 1.25GB/S NANO-TECHNOLOGICAL TRANSPONDER FOR SPACE WIRE OPTICAL/ELECTRICAL INTERCONNECTS Space-Qualified 1.25Gb/s Nano-Technological Transponder for SpaceWire Optical/Electrical Interconnects SPACE-QUALIFIED 1.25GB/S NANO-TECHNOLOGICAL TRANSPONDER FOR SPACE WIRE OPTICAL/ELECTRICAL INTERCONNECTS

More information

Introduction to VLSI ASIC Design and Technology

Introduction to VLSI ASIC Design and Technology Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics

More information

20Gb/s 0.13um CMOS Serial Link

20Gb/s 0.13um CMOS Serial Link 20Gb/s 0.13um CMOS Serial Link Patrick Chiang (pchiang@stanford.edu) Bill Dally (billd@csl.stanford.edu) Ming-Ju Edward Lee (ed@velio.com) Computer Systems Laboratory Stanford University Stanford University

More information

A 2.5V Step-Down DC-DC Converter for Two-Stages Power Distribution Systems

A 2.5V Step-Down DC-DC Converter for Two-Stages Power Distribution Systems A 2.5V Step-Down DC-DC Converter for Two-Stages Power Distribution Systems Giacomo Ripamonti 1 École Polytechnique Fédérale de Lausanne, CERN E-mail: giacomo.ripamonti@cern.ch Stefano Michelis, Federico

More information

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 77-81 International Research Publication House http://www.irphouse.com Noise Tolerance Dynamic CMOS Logic

More information

Fractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter

Fractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September

More information

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation Francesco Carrara 1, Calogero D. Presti 2,1, Fausto Pappalardo 1, and Giuseppe

More information

Synchronous Mirror Delays. ECG 721 Memory Circuit Design Kevin Buck

Synchronous Mirror Delays. ECG 721 Memory Circuit Design Kevin Buck Synchronous Mirror Delays ECG 721 Memory Circuit Design Kevin Buck 11/25/2015 Introduction A synchronous mirror delay (SMD) is a type of clock generation circuit Unlike DLLs and PLLs an SMD is an open

More information

Chip Scale Package Fiber Optic Transceiver Integration for Harsh Environments

Chip Scale Package Fiber Optic Transceiver Integration for Harsh Environments Chip Scale Package Fiber Optic Transceiver Integration for Harsh Environments Chuck Tabbert and Charlie Kuznia Ultra Communications, Inc. 990 Park Center Drive, Suite H Vista, CA, USA, 92081 ctabbert@

More information

Lecture 1, Introduction and Background

Lecture 1, Introduction and Background EE 338L CMOS Analog Integrated Circuit Design Lecture 1, Introduction and Background With the advances of VLSI (very large scale integration) technology, digital signal processing is proliferating and

More information

THE SELF-BIAS PLL IN STANDARD CMOS

THE SELF-BIAS PLL IN STANDARD CMOS THE SELF-BIAS PLL IN STANDAD CMOS Miljan Nikolić, Milan Savić, Predrag Petković Laboratory for Electronic Design Automation, Faculty of Electronic Engineering, University of Niš, Aleksandra Medvedeva 14.,

More information