The 20th Microelectronics Workshop Development status of SOI ASIC / FPGA

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1 The 20th Microelectronics Workshop Development status of SOI ASIC / FPGA Oct. 30th 2007 Electronic, Mechanical Components and Materials Engineering Group, JAXA H.Shindou

2 Background In 2003, critical EEE parts for space use were selected at the Japan space EEE parts committee in order to develop advanced space systems. Programmable device (FPGA) was selected as one of the first phase items of critical components. We started the feasibility study about FPGA based on 0.15 m m FD-SOI technology. We also started the development of SEU / SET hardened cell library for SOI ASIC. SEU: Single Event Upset SET: Single Event Transient FD-DOI: Fully depleted Silicon on Insulator FPGA: Field Programmable Gate Array ASIC: Application Specific Integrated Circuit 1

3 Why we choose FD-SOI JAXA has developed LSIs with the latest technology for commercial market. For <0.18 m technology, SEEs are main concern for LSIs for space applications. FD-SOI is attractive for space because of its SEE hardness as compared with bulk technology. (also suitable for Low power application.) Now we plan to utilize the FD-SOI as a mainstream technology. Design Rule (1/2pitch) [ m] m, 33MHz 64bitMPU(3.3V) 0.18 m, 200MHz 64bitMPU(1.8V) 0.15 m, FDSOI(1.5V) Year Design rule trend and JAXA s LSI roadmap SEE: Single Event Effect 2

4 PD-SOI vs FD-SOI (Courtesy of OKI, quoted from 19MEWS material) 3

5 Oki FD-SOI Device Structure & Process um SOI (Production line) LOCOS STI Metal (1M)/0.48(<2M) BOX 200nm 145nm Low Leakage (LL) Ioff<2E-12A/um (Courtesy of OKI, quoted from 19MEWS material) 4

6 Development schedule (SOI process) Basic Process Development (3 Metal Layers) Process Module Development for 6 Metal Layers Process Development for 6 Metal Layers Test Element Group Chips #1 (3 Metal Layers) Test Element Group Chips #2 (3 & 6 Metal Layers) Design & Chip production/ Qualification Test ASIC Cell library / Memory generator Apr May Jun Finalizing 2007 Jul Aug Sep WLR WP: Wafer Processing WP Oct Nov Dec Jan Feb Mar WLR: Wafer Level Reliability Evaluation Evaluation Design Cell library & evaluation chip WP Design Memory generator WLR 2008 Apr May Jun Final SPICE /PDK - Process development with 6 metal layers is in progress. - Final SPICE/PDK is scheduled to be released at the end of fiscal year. WP 5

7 Target Specification for ASIC / FPGA 0.15μm commercial FD-SOI foundry with patented SEU/SET free primitive circuits. (RHBD techniques used) 1.5V V for core and 3.3V for I/Os. SEU/SET free up to LET of 64MeV/(mg/cm 2 ) TID: 1kGy(Si) (100krad(Si)) ASIC & FPGA Joint development with CNES / ATMEL SRAM based re-configurable FPGA. (Based on ATMEL architecture) 700k k ASIC gates FPGA RHBD: Radiation Hardened By Design TID: Total Ionizing Dose LET: Liner Energy Transfer 6

8 Single Event Transient signal generation CMOS/Bulk Inverter Input output V DD GND p-substrate n-well p+ Input 0 V DD 1 GND Output SET Signal - e-h pair generation by an Ion strike to the OFF-state transistor - Reversed biased junctions collect charge - Voltage transients propagate appreciable distances 7

9 Advantage of SOI structure CMOS/SOI Inverter Input output V DD GND n+ BOX(SiO 2 ) p-substrate p+ Input V DD Output GND - Sensitive volume for charge collection CMOS/Bulk > CMOS/SOI - All the transistors are electrically isolated by dielectric material It is possible to eliminate the SET signal generation by implementing RHBD! 8

10 Basic concept of RHBD 1.0 A Y Redundant Tr Pairs RHBD Inverter (SET free) Error X-Section [ m 2 /bit] 対策なし ( リファレンス ) 対策あり ( エラーなし 上限値 ) LET [MeV/(mg/cm 2 )] The redundant transistor pairs completely prevent the SET pulse generations on the output terminal.this concept can be easily extended for any logic gates and the logic circuits. However the optimization of area, power, speed penalties is an important issue. Ar Conventional RHBD Inverter Kr Xe 9

11 TEG evaluation The design and evaluation (Irradiation test) of the Test Element Group are in progress.test results will be applied to the design of FPGA and Cell library. Irradiation test system (Heavy-ion accelerator at Japan Atomic Energy Agency) 10

12 Development schedule (ASIC & FPGA) Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Basic Process Development (3 Metal Layers) Finalizing WLR Process Module Development for 6 Metal Layers WLR: Wafer Level Reliability Evaluation Process Development for 6 Metal Layers Test Element Group Chips #1 (3 Metal Layers) WP: Wafer Processing WP Evaluation WLR Final SPICE /PDK Test Element Group Chips #2 (3 & 6 Metal Layers) WP Design & Chip production/ Qualification Test ASIC Cell library / Memory generator Design Cell library & evaluation chip Design Memory generator WP Test Element Group Chips #1 Configuration bits / Free RAMs for FPGA RAM cells, Shift registers for SET testing Test Element Group Chips #2 Core cells for FPGA 11