CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology

Transcription

1 CMOS Digital Logic Design with Verilog Chapter1 Digital IC Design &Technology Chapter Overview: In this chapter we study the concept of digital hardware design & technology. This chapter deals the standard chips design, programmable logic devices, full-custom and semi-custom IC design, basic design loops, structure of computer and digital hardware design units. Implementation of technology: transistor switching, NMOS, CMOS logic gates, standard chips, MOS fabrication, noise margin, dynamic and static operation of logic gates, transmission gates, implementation of SPLD, CPLD & FPGAs. Chapter Objectives : Demonstrate the concept of digital hardware design. Illustrate the implementation of technology such as transistors switching, NMOS, CMOS logic gates. Show the concept of custom IC design, standard cell and gate arrays. Demonstrate the use of programmable logic devices. Show the practical analysis of MOS devices. Objective6: Show the important MOS fabrication processes. Objective7: Demonstrate the design and applications of SPLDs, CPLDs and FPGAs. Unit1: Digital Hardware Design Demonstrate the standard & custom design chips.

2 Show the programmable logic devices. Define the full-custom and semi-custom IC design. Define the important units of digital hardware. Define the standard chips design strategies. Give the brief description of programmable logic devices. Define the difference between full-custom and semi-custom IC Design. Demonstrate the important units/ segments of digital hardware. Unit2: Transistors switching, NMOS & CMOS logic gates Demonstrate that MOS transistors function as switch, register and capacitor. Demonstrate the I D & V D characteristics of the NMOS transistors. Demonstrate the application of Transmission gates (TG) logic. Define the differences between Pseudo, Depletion and CMOS logic. Design 2-input NAND gate circuit draw the truth table and write the switching action of the transistors. Derive the drain current equation for NMOS transistors and draw the I D & V D characteristics.

3 Design the mux4:1 using Transmission gate logic. Problem 4: Prove that transistors work as switch, register and capacitor. Problem 5: Show the differences between Pseudo, Depletion and CMOS logic. Unit3: Programmable logic devices Explain the programmable logic array (PLA). Demonstrate programmable array logic (PAL). Demonstrate the programing of PLA and PAL. Define the functionality of Field programmable gate array (FPGA). Demonstrate the ability of Complex programmable logic devices (CPLD). Objective6: Show the applications of CPLDs and FPGAs. Explain the difference between PAL and PLA. Show the specific function of field programmable gate array. Demonstrate the ability of Complex programmable logic devices (CPLD). Show the applications of CPLDs and FPGAs. Unit4: Custom chips, standard cell and gate arrays Define the custom chips.

4 Show the functionality of standard cell. Define the applications of gate array. Explain the custom chips. Demonstrate the functionality of standard cell. Illustrate the applications of gate array. Unit5: MOS fabrication process Show the basic MOS fabrication process. Define n-well process. Define p-well process. Demonstrate SOI process. Show the sea of gate layout. Demonstrate the basic MOS fabrication process. Define the n-well process with suitable diagram. Demonstrate p-well process with proper steps. Demonstrate the Silicon on Insulator fabrication process. Unit6: Practical analysis of MOS devices

5 Determine the MOSFET on resistance. Show the voltage level in logic gates. Determine the noise margin in MOS devices. Demonstrate the dynamic operation of logic gates. Calculate the power dissipation in logic gates. Objective6: Demonstrate the passing 1s and 0s through transistors. Objective7: Show the concept of fan-in and fan-out in logic gates. Determine the MOSFET on resistance. Show the voltage levels in logic gates. Calculate the noise margin in the MOSFET. Show the dynamic operation of logic gates. Problem5: Demonstrate the technique for the calculation of power dissipation in MOS devices. Problem6: Demonstrate the passing 1s and 0s through transistors. Problem7: Show the concept for calculation of fan-in and fan-out in logic gates. Unit7: Implementation of SPLD, CPLD and FPGA Demonstrate the physical implementation of SPLDs.

6 Define the work function of CPLDs. Demonstrate the physical implementation of FPGA. Illustrate the difference between SPLD, CPLD and FPGA. Demonstrate the practical picture of SPLDs. Show the design and function of CPLDs. Illustrate the basic difference between SPLDs, CPLDs and FPGAs. Chapter Level problems: Demonstrate the digital hardware design. Show the construction flow of programmable logic devices. Show the applications of SPLDs, CPLDS and FPGAs. Demonstrate the pictorial layout and its monograph of CMOS Inverter. Chapter Learning Strategies: