Component Miniaturization and High-Density Technologies in Space Applications

Transcription

1 Component Miniaturization and High-Density Technologies in Space Applications Norio NEMOTO Parts Program Office Safety and Mission Assurance Department JAXA 2014/10/23 MEWS 27 1

2 1. JAXA EEE Parts Organization JAXA EEE Parts organization has been changed on 1 st April 2014 Senior Chief Officer, Space Eng. Yasuyuki ITO Research Promotion Department Ryoichi IMAI Electronic Devices and Materials Group Koichi SUZUKI Research and Development of Space Parts & Technology Development of the strategic EEE parts R&D for the advanced technologies Senior Chief Officer, S&MA Nobuo TAKEUCHI Safety & Mission Assurance Dept. Tatsushi IZUMI Parts Program Office Norio NEMOTO Qualification and Engineering Support regarding EEE components Promoting utilization of JAXA Qualified parts Cooperation with foreign entities Improvement of imported part procurement JAXA Alert/anomaly investigation support Utilization technology research (lead-free soldering, High-density package soldering) 2014/10/23 MEWS 27 2

3 2. Basic Tactics of JAXA Parts Program 2014/10/23 MEWS 27 3

4 2. Basic Tactics of JAXA Parts Program (1) Development of strategic EEE parts (strategic EEE parts : the high- function and high-intensity IC, etc.) for maintain independence and ensure acquisition of necessary performance of the space system (2) Cooperation with foreign entities Improving independence of ITAR by cooperating with European countries (3) Improvement of imported parts procurement (ensuring the quality of the imported parts) (4) Promoting utilization of JAXA Qualified parts (5) R&D for the advanced technologies (challenging for the breakthrough) 2014/10/23 MEWS 27 4

5 Tactics #1 Development of the strategic parts to upgrade JAXA space systems Using domestic technologies, JAXA maintains independence and ensures acquisition of necessary performance of the space system. (1) Improving independence a) To improve independence, the share (usage percentage) of JAXA Qualified parts used in the space systems shall be increased. Our target is to increase the share of JAXA Qualified parts by 10% at the end of the 10 year period (in terms of parts type used by satellite projects). b) To achieve improvement, the strategic parts will be developed and the utilization of the JAXA Qualified parts will be enhanced. 2014/10/23 MEWS 27 5

6 Tactics #1 Development of the strategic parts to upgrade JAXA space systems (2) Developing the parts with 4H characteristics(high speed, Huge capacity, High density, and High efficiency) a) High speed and Huge capacity devices within 10 years MPU for space use : target is 1 GIPS(Giga Instructions Per Second) Mixed signal SOI-ASIC Program devices used for high speed digital circuit also be developed. b) High density, and High efficiency Downsizing/SMD of passive parts and improvement of efficiency in power devices shall be promoted. By 2022, the mounting area of the equipment with the performance equivalent to the current equipment shall be 2014/10/23 reduced in half. MEWS 27 6

7 Tactics #5 R&D for the advanced technologies Seek the revolutionary technology development that could transform the concepts of components to ensure independence in the future. (1) Compound semiconductors, etc. For GaN element, the Ka-band high power type output step element for the high output microwave amplifier shall be developed by FY /10/23 MEWS 27 7

8 Tactics #5 R&D for the advanced technologies (2) High density mounting process Based on the experience of evaluation about the BGA and CGA, BGA/CGA Mounting Technology Requirements (JERG-0-054) was established in FY2013. Continuing module manufacturing with 3D mounting and assessment/test researches, the basic technologies that can be used for flight products shall be established by FY2017. (3)Micro Electro Mechanical Systems (MEMS) devices Assessment of environment/radiation tolerance is promoted, while process technologies acquisition for independent development shall be pursued. The results of these activities shall be used to identify the applicability to parts development and applied to the actual flight hardware development. 2014/10/23 MEWS 27 8

9 3. Miniaturization and High-Density Technology 2014/10/23 MEWS 27 9

10 Trend of Space Application Miniaturization, high density, high performance and high efficiency are required for next generation space application. High Performance, High Functionality High Accuracy Multiple Functions Miniaturization High-Density High-Capacity Speeding Up Low Power Consumption Miniaturization and High-Density involves many technology Weight Saving Miniaturization, High-Density 2014/10/23 MEWS 27 Low-Heat- Generating High Efficiency 10

11 4. Example of Device under Development for Miniaturization and High-Density 2014/10/23 MEWS 27 11

12 1. Mixed signal SOI-ASIC (1/2) Status : Element evaluation Concept for the System On Chip ADC, DAC, Analog Multiplexer, Regulator, PWM with domestic technology SOI technology for radiation-hardened and low-power consumption NOW: ADC sample testing By 1 st Q 2016: QT sample will be prepared MPU DSP RAM Mixed signal SOI-ASIC ADC DAC Concept image System on chip 2014/10/23 MEWS 27 12

13 1. Mixed signal SOI-ASIC (2/2) Target specification Description Process 0.15um, 6 layer, SOI Input voltage core 1.5V, I/O 3.3V Storage Temp. chip size Analogue IP Digital IP D-FF toggle f. Power consumption -55 to +125 degree C 10 x 10 mm (max) Target capability ADC (sampling speed 50MHz, resolution 12bits) [Nvt / Lvt] 42 type sequential, 293 type combinational circuit, I/O buffer, Single-port SRAM GHz(Nvt), GHz(Lvt) (two NANDs) nw/mhz (Nvt), 15.0 uw(lvt) SEU LET > 64 [MeV/(mg/cm 2 )] SEL immune TID 1000 Gy(Si) 13

14 2. High-Density Assembly About the realization of miniaturization and high-density of the system component, harmonization of package (device) technology, PCB technology and inspection technology are required. Package Technology (BGA) BGA Package : Element evaluation phase Printed Circuit Board : Qualified in Jan. 31/2014 Miniaturization, High-Density BGA/CGA Mounting Technology Requirements (JERG-0-054): Established in July 22/2013 PCB Technology Assembly and Inspection Requirements 14

15 2.1 BGA Package and Mount Technology (1/2) Status : Element evaluation Target feature Remark TYPE C-BGA (26x26mm) Al 2 O 3 Pin count x24 (no 4-corner-pins) Ball pitch 1.0 mm Ball material Solder 63Sn/37Pb or 10Sn/90Pb with a vacuum reflow Wire bonding Al wire-bonding conventional process Mount tech. BGA with/without underfill Assembly Area 1/3 of 304 pin CQFP C-BGA package without seal-cap (top-side) C-BGA package (bottom-side) 304pin CQFP pin CBGA

16 2.1 BGA Package and Mount Technology (2/2) Evaluation status Item Wire bonding Status Good with conventional wire-bonding method Ball attach Good with a vacuum reflow oven (void less) PKG Mounting Thermal shock test (-30 to +100 degree C) (without underfill) 631 cycles (with underfill) 1,046 cycles for effective I/O pins More analyses and examinations will be performed. Development phase will start in the 4th QT of FY2014 and finish in FY2016 (target). 16

17 2.2 Printed Circuit Board for Area Array Package (1/2) Pitch 1.27mm Pitch of via hole = 1.0mm Design for 1.0mm pitch via hole, two signal lines and Via in Pad. Conductor Width =0.08mm A Via Drill Diameter =0.20mm Land Diameter =0.45mm Soldering Pad Conductor width =0.13mm Conductor Spacing =0.08mm Conventional design rule A Via Drill Diameter =0.35mm Land to Conductor spacing =0.155mm VIP 1.0mm Via in Pad Via hole Land Diameter Land to Conductor Spacing =0.75mm =0.195mm 2014/10/23 MEWS Conductor Width and Spacing=0.08mm/0.08mm Cross section of A-A

18 2.2 Printed Circuit Board for Area Array Package (2/2) Item PCB Specification Target Package QFP Area Array PKG Pad Pitch 1.27mm 1.0mm Structure Fan out of Pad Fan out of Pad Via-in-Pad Drilled hole diameter 0.35mm Dia. 0.20mm Dia. Conductor (Internal) Number of Layers(Max.) Board thickness Width 0.13mm 0.08mm Spacing 0.18mm 0.08mm Total Blind via 8 6 Modified Polyimide 2.4mm 2.1mm FR-4 1.6mm NA HTg FR-4 NA 2.3mm Surface finish HASL* HASL* *HASL: Hot Air Solder Leveling 2014/10/23 MEWS 27 18

19 2.3 BGA/CGA Mounting Technology Requirements Area array package is different from traditional device because of its leadless feature. JAXA established new mounting technology requirements for BGA and CGA. This requirements include quality assurance and assembly process for BGA and CGA. 1. Quality Assurance Method 2. Assembly Process and Inspection Method Established for BGA and CGA 3. Control Point for BGA and CGA Product Production 4. Rework 2014/10/23 MEWS 27 19

20 5. Conclusion The strategic parts are under Development. To contribute to reduce the size and weight of space application, miniaturization and high-density device is required. The following are the development devices in pursuit of Miniaturization and High-Density; Qualified Printed Circuit Board for Area Array Package Basic evaluation BGA Package and Mount Technology Mixed signal SOI-ASIC 2014/10/23 MEWS 27 20