Innovations Push Package-on-Package Into New Markets. Flynn Carson. STATS ChipPAC Inc Kato Rd Fremont, CA 94538
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1 Innovations Push Package-on-Package Into New Markets by Flynn Carson STATS ChipPAC Inc Kato Rd Fremont, CA Copyright Reprinted from Semiconductor International, April By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
2 Innovations Push Packageon-Package Into New Markets Package-on-package (PoP) technology is evolving and advancing to meet the challenges of higher integration and performance in the smaller form factors required by the mobile market. Solutions are transitioning to flip-chip and finer package-to-package interconnects. Flynn Carson STATS ChipPAC Inc., Singapore, Package-on-package (PoP) has become the preferred method to integrate logic and memory for advanced mobile phone platforms that find their way into high-end mobile handsets and smart phones. The mobile handset industry is poised for positive growth after the downturn in 2009 and, as the market rebounds, smart phones are projected to have much higher growth than other phone segments and garner an increasing share of the market. PoP solutions are also finding their way into other mobile Internet devices and portable media players. This translates into a greater demand for PoP solutions to be the engine that supports the ever-increasing complexity and features required for such devices. The market leaders for application processors and baseband/application processor combinations, which are at the heart of these feature-laden devices, all use or plan to use PoP solutions (Fig. 1). PoP technology evolution For the bottom PoP package, the transition from wire bond to flip-chip is happening quickly. The need for smaller package size is driving finer ball pitch, and Wire bonds are still cost-effective and being used in PoPs, although a shift is taking place toward flip-chip. mm ball pitch on the bottom PoP is now commonplace. Meanwhile, the need for higher-speed and higherbandwidth DRAM, and DRAM with flash memory in the top package is driving the need for higher ball count for the top package. Higher ball counts and reduced package size requirements are necessitating finer ball pitch for the top package. Whereas 0.65 mm pitch may have been adequate in the past, now 0.5 mm pitch is required and 0.4 mm pitch is on the horizon. This reduction in the package-to-package ball pitch has many implications. Finer pitch translates to smaller solder ball sizes and stand-off height of the top package after reflow on top of the bottom package. Of course, this affects the height allowance for the device housed in the bottom package. Most of the innovation Semiconductor PACKAGING 17
3 Innovations Push Package-on-Package Into New Markets and advancements being worked on today are to enable this transition to flip-chip and finer package-to-package interconnect to realize the market need for reduction in package size and stacked height (Fig. 2). Taking a step back, while the transition from wire bond to flip-chip is clearly underway for the bottom package that houses the logic processor, wire bond is not dead and is still the standard interconnect method for the memory devices in the top package. Wire bond is still cost-effective, especially if copper wire is used, and is required to integrate stacked devices in the bottom package, which is still a requirement for a subset of bottom packages. The wire-bonded bottom package is encapsulated using top-center-mold gate (TCMG) molding technology to leave the periphery Package size of the bottom package free (mm/side) of epoxy mold compound Stacked PoP (EMC) so the land pads on height (mm) the top periphery are exposed to allow top package Min. ball pitch, bottom PoP (mm) interconnect. The thickness of this mold cap must cover Min. ball pitch, the die and the wire loops top PoP (mm) above the die surface. If the top package pitch is reduced from 0.65 mm to 0.5 mm, it becomes a challenge to mold the wire-bonded device within the required 0.22 mm mold cap height. The bond shell or area at the periphery of the die required for wire bond also becomes a stumbling block to reducing package size. Although some applications such as those requiring stacked die or applications targeted at the mid-range segment of the mobile market may stay in wire-bond TCMG bottom package, the majority of future applications will transition to flip-chip to enable smaller packages, top package pitch and higher density and performance. Flip-chip bottoms Development and introduction of the flip-chip bottom package can be categorized into two main types: baredie type and over-molded type. The bare-die flip-chip bottom package is essentially like a thin miniaturized flip-chip BGA. The current sweet spot for PoP size is no larger than mm, and preferably mm with 0.5 mm ball pitch between packages. The bare-die flip-chip bottom package has already been developed and introduced into mass production to meet these requirements. To do so, the mounted height of the flip-chip device must be ~0.18 mm. This can be accomplished by thinning the flip-chip device down to 0.10 mm, which is well within current capability. A main concern is controlling the warpage of the package during reflow. During the surface-mount (SMT) process, the bottom package is placed on solder paste that has been stenciled on the PCB, then the top package is dipped in flux and placed on top of the bottom package; the two packages are then reflowed simultaneously to the PCB (as are all other components mounted on the Package-on-Package Trends <17 <15 <14 <12 <1.8 <1.6 <1.4 < / /0.32 PCB) as they go through the reflow furnace. All PoPs currently in production use lead-free solder balls, so reflow temperatures can peak at 260ºC with no nitrogen flow in the furnace. The SMT process needs to be robust enough to realize very low defects per million (DPM) yield levels hence the need to control PoP warpage tightly during reflow to allow for the highest possible yields. For 0.5 mm package-to-package ball pitch, the desired warpage during reflow of either package is <0.06 mm. This target can be met by selecting the right substrate thickness and core material, especially for the mm size. For the mm size, this becomes more of a challenge, which can be met by implementing substrate core materials with a low coefficient of thermal expansion (CTE). There has been a flurry of activity among substrate material suppliers to introduce low-cte laminate substrate materials to meet requirements. 2. As PoP technology evolves, size, height and ball pitch trends are emerging. Large-body solutions Over-molded bottom PoPs are being driven by body sizes that are larger than mm with 0.5 mm top ball pitch and the migration to 0.4 mm top ball pitch (Fig. 3). Such over-molded bottom PoPs can also accommodate die stacking, including wire-bonded devices Semiconductor PACKAGING 19
4 Innovations Push Package-on-Package Into New Markets Package-on-Package Solutions Bare die flip-chip Over-mold w/mech. cut Over-mold w/laser via stacked on top of flip-chips. The over-molded bottom PoP is array-molded and saw-singulated like conventional fine-pitch ball grid array (FBGA) packages, so the EMC extends to the package edge and can help control package warpage. The obvious issue is how to expose the top peripheral land pads to allow for the interconnection via solder balls to the top package. Two methods have so far been developed to accomplish this: mechanical cut and laser ablation. Mechanical cutting can be used to remove the EMC above a solder ball, which has been mounted on the top peripheral lands of the bottom package prior to over-molding. This leaves the EMC thinner at the package edge, but the solder ball exposed to allow reflow of the top package. The height or thickness of the EMC material at the peripheral edge has to be very precisely controlled as it impacts the exposed solder ball diameter, solder volume and quality of the solder joint to the top package after re- 3. There are several PoP solutions for finer interconnect pitch, including bare-die flip-chip, overmold with mechanical cut, and over-mold with laser via. flow. This type of bottom PoP has been developed, but hasn t been widely adopted yet. More focus is being drawn by the over-molded bottom PoP type that uses laser ablation to expose solder balls mounted to the top peripheral lands of the package. The use of laser ablation or drilling has become widespread to make vias in package substrate manufacturing and is now being leveraged to make vias in the EMC in the bottom package. Again, control of the via formation is critical to enable defect-free reflow of the top-to-bottom PoP during SMT. The alignment of the via to the solder ball as well as the outer-hole diameter (OHD) at the top of the mold cap and the inner-hole diameter (IHD) where the laser-via intercepts the solder ball all must be optimized and tightly controlled. Such capability has been demonstrated for 0.5 mm package-to-package ball pitch and many large-volume (sample size) SMT trials, and board-level reliability studies are underway to prove acceptable DPM levels. The 0.4 mm package-to-package ball pitch is also being developed for this laser-via type of bottom package. For 0.4 mm package interconnect ball pitch, the warpage budget or allowance must be reduced to <0.05 mm. The over-molded laser-via type combined with low-cte substrate is being developed to meet this requirement. Future Package-on-Package Solutions Fan-in PoP Super thin TSV PoP ewlb PoP 4. Future PoP solutions will continue to enable higher density and thinner stacks. 20 Semiconductor PACKAGING
5 Innovations Push Package-on-Package Into New Markets Bare-die flip-chip bottom PoP can be considered, but to accommodate the lower standoff of the 0.4 mm package interface pitch, the flip-chip device would need to be thinned to ~0.06 mm to have a mounted height of ~0.13 mm. Handling and testing of such thin bare-die flip-chip devices is a major concern. However, bare-die flip-chip PoP has the lowest assembly cost structure. The majority of the focus to enable 0.4 mm PoP interface pitch is on the laser-via type and it is envisioned that molded underfill (MUF) of the flip-chip as well as other low-cost flip-chip methodologies can be developed and used to reduce the cost of this package over time. PoP for the future The need for smaller and thinner PoP solutions will continue, and it is anticipated that PoP will find its way into products beyond the current market segments into lowercost mobile phones and other consumer devices. Thinner PoP solutions to enable finer PoP interconnect pitches are being developed to address these needs (Fig. 4). Thinner, high-density substrates, matching more closely the material properties of the silicon devices themselves to minimize warpage, are also being evaluated. Even the use of silicon-based substrates with through-silicon vias (TSVs) is being explored to enable super-thin PoP stacks. TSV can achieve thin high-density memory stacks that may be deployed in the top PoP memory stack in the near future. The fan-in PoP has already been developed to enable high-density fine-pitch package-to-package interconnect (0.4 mm top package pitch already demonstrated). Next-generation 3-D fan-out wafer-level package (FOWLP) technology, most notably the embedded wafer-level BGA (ewlb), is being developed to enable extremely thin PoP building blocks. Such an ewlb package with redistribution layers on both sides of the package and vias made through the plastic fan-out area at the package periphery can enable package body thickness of ~0.25 mm, side-by-side die within the package body, and high-density package interfaces with <0.4 mm pitch, thereby allowing package-to-package gaps of <0.15 mm. With such technology, the goal of PoP with <1.0 mm height and <12 12 mm package size can be realized. SI Flynn Carson is vice president of technology marketing at STATS ChipPAC, responsible for new product and technology introduction, especially in the area of advanced 3-D packaging and advanced integration technology. He has a B.S. in mechanical engineering and material science from the University of California, Davis. 22 Semiconductor PACKAGING
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