The Design Challenge to Integrate High Performance Organic Packaging into High End ASIC Strategic Space Based Applications.

Transcription

1 The Design Challenge to Integrate High Performance Organic Packaging into High End ASIC Strategic Space Based Applications May 8, 2007

2 Abstract: The challenge to integrate high-end, build-up organic packaging like CoreEZ into strategic space based applications will push the substrate fabrication and design into an area that offers performance - electrical, thermal and reliability that is second to none. Designing a system with dozens of ASICs and challenging the substrate design and fabrication team to produce packages that meet the needs of systems electrical requirements while offering robust performance is a large task. In addition, requiring the design team to integrate common features among a plethora of common applications is a challenge that is formidable yet not without possibilities that the Endicott Interconnect first level CoreEZ packaging technology is capable of producing. The Endicott Interconnect legacy of drilling 50 micron through vias at an average rate of over 200,000 vias per panel is a testament to the robustness and reliability of the technology here in Endicott. Applications with this technology have included not only high end 24/7/365 applications in a range of high- end demanding server customers, but have also included customers as demanding as the Department of Defense. Many of these DoD applications have included a set of design parameters that most ceramic applications have been able to achieve only with increased layer count, greater weight, front end NRE s and second level interconnect reliability that is often challenged through larger packages using ceramic column grid arrays (CCGA). Many of these high end System-in-Package (SiP) applications contain a central processing ASIC surrounded by high speed memory sometime utilizing a combination of both flip chip and wire bond devices on the same design. The capability for CoreEZ to offer high performance packaging, where signals are maintained in a full strip-line environment, a low profile substrate cross section, as well as the capability to drill 50 micron through vias on a sub 200 micron pitch within the core will allow the power distribution needs and the thermal dissipation requirements of the ASIC to be met per the system specifications. At the same time, the system engineer will benefit from reduced weight and a smaller overall footprint for the entire Si80P assembly.

3 Application Drivers for Semiconductor Package Selection ƒwireability ƒelectrical Performance ƒpower ƒreliability ƒprice 9

4 Why use buildup? What is CoreEZ? It's a THIN CORE semiconductor substrate with ULTRA FINE CORE VIA PITCH Thin core provides: Outstanding signal performance, near transparent package performance Outstanding wireability clean eye s at 10Gb/s Outstanding power and ground distribution performance Lower noise Additional vias for power and ground connections Very dense core via pitch allows 2X wiring OR reduced layer count Materials compatible with Strategic based application needs

5 Typical Thin Core 10 layer Cross Section - CoreEZ Gnd / Top S1 Pwr / Gnd S2 Pwr / Gnd Pwr / Gnd S3 Pwr / Gnd S4 Gnd / Bot Solder mask PSR µ thick Copper-filled stacked micro-via Substrate Thickness 0.55 mm Solder mask PSR µm thick Build up layer 1 Build up layer 2 Build up layer 3 DriClad, 35/50 µm thick Outer Core dielectric DriClad, 35/50 µm thick Inner Core 100/150µm thick Core Cu 12 µm thick Build up Cu 1 Build up Cu 2 Build up Cu 3 12 µm thick

6 Substrate Product Options Availability Single chip or System In Package With or without stiffener (Cu or SS) Description = 2 full stripline signal planes = 4 dual stripline signal planes = 4 full stripline signal planes Stacked Buildup vias 50 & 35 micron BU thickness Core 2 layer 50 micron core Layers: Up to 12 (4-4-4, 4 full stripline signal) Lead free compatible Ultimate in design flexibility

7 CoreEZ Reliability Test Vehicle Description 42.5mm body size 14.7mm die size High melt flip chip bump 225µm die pad pitch, internal wiring supports 150µm die pad pitch 8 layer (2-4-2) cross section EIT has successfully reached 5000 cycles of o C accelerated thermal cycling (component assembled to PWB) No die cracking, no BGA or bump fatigue Component level testing -55 to +125 o C has successfully reached 1000 cycles Customer Quals standard SCM and SIP application qualifications underway

8 Evaluation of Materials Subjected to Radiation Levels Evaluated PTFE and CoreEZ materials radiation response Radiation Exposure: Co60 Gamma: Control & various levels krad TID PTFE Substrates Materials Considered: Rogers 2800, Asahi APPE, Pyralux FR Results: Many applications will be unaffected by radiation APPE & Pyralux have no measurable degradation to 5 Mrad R2800 shows gradual loss of ductility with exposure CoreEZ Materials Considered: Thermount, Driclad, PSR4000 Results: No measurable change of mechanical properties through 5 Mrad Update: Refined application estimate for HyperBGA usage Considered 11mm die size, no lid, usage temp delta 40C, on thick card 18ppm/C Used model / test bridge from previous low-ductility qualification testing Projection: After 500krad exposure, expect 17,500 cycles to N50 failure

9 Radiation Tolerance Summary Percent Ductility vs TID exposure All CoreEZ materials tested beyond Strategic level radiation tolerance HyperBGA- PTFE material good thru Tactical level tolerance Rad Rad Strategic TolerantHard 300 1Mrad 100krad krad Beyond 5M CoreEZ PSR mask CoreEZ Driclad buildup CoreEZ Tmount core Hyper Pylux adhes Hyper APPE outer Hyper PTFE inner

10 Electrical Design Considerations

11 High Speed SERDES in CoreEZ Layup Representative Differential Pair Routed on S4 (not to scale) Layer Top S1 S2 Power Power S3 S4 Bot Typical Function Pads / Voltage / Gnd Stripline Signal Voltage / Gnd Voltage / Gnd Voltage / Gnd Voltage / Gnd Stripline Signal Pads / Voltage / Gnd

12 High Speed SERDES in CoreEZ Differential Pair Design Representative Differential Pair Routed on S4 Feature Z0 differential mode Pair Length Die pad pitch Die pad diameter Power Plane Thru-hole Signal dog bone length / width Signal line Width / Space Signal die pad uvia Signal BGA pad uvia BGA pad pitch BGA pad diameter Value 100 ohms 18.5 mm 190 µm 150 µm 162 µm 75 / 90 µm 34 / 80 µm 100 µm 150 µm 1.27 mm 800 µm

13 High Speed SERDES in CoreEZ Differential Mode S-Parameter Extraction Ansoft HFSS TM Model Extracted from Cadence Allegro TM with AnsoftLinks TM Die Pad Port Launch Details BGA Port Launch Details

14 High Speed SERDES: CoreEZ 12.5 Gbps Eye Diagram Simulation 300 mv 55 ps Zoom for jitter

15 High Speed SERDES in CoreEZ 12.5 Gbps Eye Diagram Simulation jitter ~2.2 ps

16 CoreEZ 4-4-4, 35µm Dielectric and Stacked Via Additional layers result in minimal degradation of insertion loss Dogbones provide only a slight disadvantage over stacked vias, so both features are acceptable for performance goals Additional design optimizations will further enhance high speed SERDES performance

17 Recommended Package Design Considerations Maintain regular dialogue with ASIC design team Utilize a reasonable ( µm) flip chip pitch at the silicon Align common flip chip pads in rows or columns Allow package designers to assign module I/O Maintain JEDEC form factors Utilize a 1.00 mm or 1.27 mm BGA pitch For intensive high speed SERDES applications, spread them evenly around the ASIC Maintain nominal impedance values at ohms for SE and 100 ohms diff pair Establish module power and/or ground BGA s directly beneath the silicon Give up front consideration to decoupling capacitor quantity and location

18 Alignment of Common Flip Chip pads High Performance Footprint 14

19 CoreEZ vs Ceramic Via Inductance Comparison on a 40 mm MCM

20 Layup Assumptions CoreEZ Via Assumption Via Diameter: 50 um Via Pitch: 200 um Solid Copper BGA Pitch 1.27 mm Note: Via Pitch applies to via-via spacing with multiple vias per BGA HiCTE Via Assumption Via Diameter: um Via Pitch: 250 um Solid Copper BGA Pitch 1.27 mm

21 y CoreEZ vs Ceramic Via Inductance Comparison 40 mm MCM Via Spacing Assumptions y y Via BGA x x x y 1 Via / BGA y 3 Vias / BGA 5 Vias / BGA x x (drawings not to scale) 2 Vias / BGA 4 Vias / BGA

22 CoreEZ vs Ceramic Via Inductance Comparison 40 mm MCM l3d* 3D Partial Inductance Calculator Loop Inductance from VSS BGA up to VSS plane, VDD18 plane down to VDD18 BGA No plane inductance included VSS Plane VDD18 Plane L-loop (VSS-VDD18) VSS BGA VDD18 BGA

23 CoreEZ vs Ceramic Via Inductance Comparison Conclusion =>> Only One Via per BGA is required in CoreEZ

24 Selection Methodology ƒchip Footprint and Wireability If chip is I/O bound, evaluate wiring Chip size for each package can be determined Package $ vs chip $ tradeoff can be determined ƒelectrical & Thermal Requirements ƒcompare to Package Capabilities ƒreliability Requirements ƒreview Application Use Conditions ƒtemperature Excursions ƒon-off Cycles 21