EE141- Spring 2004 Digital Integrated Circuits

Transcription

1 EE141- Spring 2004 Digital Integrated Circuits Lecture 27 Power distribution Resistive interconnect 1 Administrative Stuff Make-up lecture on Monday 4-5:30pm Special office hours of Prof. Rabaey today 5-6:30pm at BWRC Homework 9 posted due next Th 5pm Poster presentations next Tu. Sign up for time slot (office door of Prof. Rabaey). Poster template on web-site. 2 1

2 Class Material Today s lecture Power distribution RC Interconnect optimization 3 Power Distribution 4 2

3 Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates 5 RI Introduced Noise V DD I f pre X R9 V DD 2 DV9 DV M 1 I R DV 6 3

4 Resistance and the Power Distribution Problem Before After Requires fast and accurate peak current prediction Heavily influenced by packaging technology Source: Cadence 7 Power Distribution Low-level distribution is in Metal 1 Power has to be strapped in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on straps 8 4

5 Power and Ground Distribution V DD GND Logic Logic V DD V DD GND (a) Finger-shaped network GND (b) Network with multiple supply pins 9 3 Metal Layer Approach (EV4) 3rd coarse and thick metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 Courtesy Compaq 10 5

6 4 Metal Layers Approach (EV5) 4th coarse and thick metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing Metal 4 Metal 3 Metal 2 Metal 1 Courtesy Compaq 11 6 Metal Layer Approach EV6 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance RP2/Vdd Courtesy Compaq Metal 4 Metal 3 RP1/Vss Metal 2 Metal

7 Electromigration (1) Limits dc-current to 1 ma/µm 13 Electromigration (2) 14 7

8 The Impact of Resistivity T r The distributed rc-line R 1 R 2 R N-1 R N C 1 C 2 C N-1 C N V in Diffused signal propagation Delay ~ L 2 voltage (V) voltage (V) x= L/10 x= L/10 x = L/4 x = L/4 x = L/2 x = L/2 x= L x= L time (nsec) time (nsec) 15 d The Global Wire Problem Challenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions Use of fat wires Insert repeaters but might become prohibitive (power, area) Efficient chip floorplanning Towards communication-based design How to deal with latency? Is synchronicity an absolute necessity? w w ( + ) T = 0.377R C R C R C + R d out d w w C out 16 8

9 Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: Tins ρ = 2.2 µω-cm M6 Increasing die size and device count: we need more wires and longer wires to connect everything W S M5 Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC H M4 3.5 Minimum Widths (Relative) 4.0 Minimum Spacing (Relative) substrate M3 M2 M1 poly 0.25 µm wiring stack µ 0.8µ 0.6µ 0.35µ 0.25µ M5 M4 M3 M2 M1 Poly µ 0.8µ 0.6µ 0.35µ 0.25µ M5 M4 M3 M2 M1 Poly Interconnect Projections: Copper Copper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2 µω-cm vs. 3.5 for Al(Cu) 40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97) Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95) Vias 18 9

10 Diagonal Wiring destination diagonal y source x Manhattan 20+% Interconnect length reduction Clock speed Signal integrity Power integrity 15+% Smaller chips plus 30+% via reduction Courtesy Cadence X-initiative 19 Reducing RC-delay Repeater 20 10

11 Repeater Insertion (Revisited) Taking the repeater loading into account For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer! 21 INTERCONNECT Dealing with Inductance 22 11

12 L di/dt V DD V in L V DD i(t) V out Impact of inductance on supply voltages: Change in current induces the change in voltage Longer supply lines have larger L C L GND L 23 L di/dt: : Simulation 5.0 v out 5V t V out (V) t fall = 4 nsec t fall = 0.5 nsec i L 40mA 20mA t I L (ma) v L V t V L (V) t (nsec) Signals Waveforms for Output Driver connected To Bonding Pads (a) v out ; (b) i L and (c) v L. The Results of an Actual Simulation are Shown on the Right Side

13 Choosing the Right Pin Bonding wire L Chip Mounting cavity L Lead frame Pin 25 Decoupling Capacitors 1 Board wiring Bonding wire SUPPLY C d CHIP 2 Decoupling capacitor Decoupling capacitors are added: on the board (right under the supply pins) on the chip (under the supply straps, near large buffers) 26 13

14 De-coupling Capacitor Ratios EV4 total effective switching capacitance = 12.5nF 128nF of de-coupling capacitance de-coupling/switching capacitance ~ 10x EV5 13.9nF of switching capacitance 160nF of de-coupling capacitance EV6 34nF of effective switching capacitance 320nF of de-coupling capacitance -- not enough! Source: B. Herrick 27 (Compaq) EV6 De-coupling Capacitance Design for Idd= 25 Vdd = 2.2 V, f = 600 MHz 0.32-µF of on-chip de-coupling capacitance was added Under major busses and around major gridded clock drivers Occupies 15-20% of die area 1-µF 2-cm 2 Wirebond Attached Chip Capacitor (WACC) significantly increases Near-Chip decoupling 160 Vdd/Vss bondwire pairs on the WACC minimize inductance Source: B. Herrick 28 (Compaq) 14

15 EV6 WACC 389 Signal VDD/VSS Pins 389 Signal Bondwires 395 VDD/VSS Bondwires 320 VDD/VSS Bondwires WACC Microprocessor Heat Slug 587 IPGA Source: B. Herrick 29 (Compaq) Design Techniques to address L di/dt Separate power pins for I/O pads and chip core Multiple power and ground pins Position of power and ground pins on package Increase tr and tf Advanced packaging technologies Decoupling capacitances on chip and on board 30 15

16 Memory 31 Issues in Memory Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies 32 16

17 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM 33 Memory Timing: Definitions 34 17

18 N wor ds De co de r EE141 Memory Architecture: Decoders M bits M bits S 0 S 1 S 2 Word 0 Word 1 Word 2 Storage cell A 0 A 1 S 0 Word 0 Word 1 Word 2 Storage cell S N2 2 Word N2 2 A K2 1 Word N2 2 S N2 1 Word N2 1 K 5 log 2 N Word N2 1 Input-Output (M bits) Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Decoder reduces the number of select signals K = log 2 N 35 Array-Structured Memory Architecture 36 18

19 Block31 Block30 Subglobalrowdecoder Global rowdecoder Subglobalrowdecoder Block1 128KArayBlock0 Local rowdecoder EE141 Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings 37 Block Diagram of 4 Mbit SRAM Clock generator Z-address buffer X-address buffer Predecoder and block selector Bit line load Transfer gate Column decoder Sense amplifier and write driver CS, WE buffer I/O buffer x1/x4 controller Y-address buffer X-address buffer [Hirose90] 38 19