Power Supply Networks: Analysis and Synthesis. What is Power Supply Noise?

Transcription

1 Power Supply Networs: Analysis and Synthesis What is Power Supply Noise? Problem: Degraded voltage level at the delivery point of the power/ground grid causes performance and/or functional failure Lower supply voltage slows the circuit down Lower supply voltage can inhibit switching and loss of state Voltage fluctuation causes noise injection in the circuit L R X C VDD GND Circuit Switching 1

2 Logic Failure due to R drop V DD φ pre R V DD - V X V V R Trends Process shrin: increased current density Lower supply voltage: decreased voltage margin ncreased frequency: rate of change of current increases ncreased complexity: large die size increases the routing length of power supply New pacaging methods: new bonding mathods (flip-chip bump) improves the drops 2

3 ssues in PSN Analysis On-chip resistance (R) and inductance (L) for P/G networ Worst case noise does not correspond to average current, or pea current Small things add up Each gate draws a small current pulse when switching Switching events and their spatio-temporal correlation Find the simulation trace that creates a switching pattern in the design resulting in the worst case voltage drop at the specific location in the grid Conservative: Approach must err on the side of predicting too much voltage drop Design Planning Chip planning will occur before a definite floorplan Current is estimated based on chip area Assume a equal distribution of power sources and power grid 3

4 Early Analysis nitial floorplan and global power grid are complete Global power grid is extracted with R s, L s, and C s Each bloc is modeled as a single current source based on an estimated DC-value or on the gate level implementation Late Analysis Both global and local power grids are extracted Current sources are modeled at the transistor or gate level 4

5 Simulation Method Decouple simulation of interconnect from the circuit Characterize the switching current of a gate/transistor Sampling frequency allows for run-time/accuracy trade-off Use a switch-level or gate-level simulator to generate switching events teration allows for reduced conservatism ssues of Simulation Method Strengths: Accuracy of model Simple integration with existing tools Weanesses: Simulation speed is not adequate for full chip microprocessor designs Confidence of covering the worst case event with a test vector is not nown Large test vectors are needed, resulting in long run times 5

6 Static Approach Model the current for a bloc/gate for a single cloc cycle Use timing windows from timing analysis to model gate switching Apply gate switching current for the entire duration of the window Sum current of each gate to obtain a bloc current for early analysis mproved Window Generation 6

7 ssues in Static Analysis Strengths: Very short run times Conservative formulation Weanesses: Topological correlation between switching is lost Switching current is applied over the entire window Statistical Approach Based on a user specified confidence level, calculate the worst case current as a function of time, using: Switching intervals of the nodes in the circuit Switching probabilities of each node Gate current characterizations 7

8 Problem Formulation Gate-level circuit implementation & P/G topology? Estimation of the worst case P/G noise Technology library containing standard cells implementation Find out worst case input pattern that triggers worst case P/G noise Proposed Methodology Cells Precharacterization Spatio-temporal nformation of Switching events Delay & Switching Current Waveform Event-driven Simulator MC, GA nput Vector Generation Noise Sampling & Noise Waveform Update so-far worst case Noise & input vector Worst case Noise 8

9 nput Vector Generation Monte Carlo is used to generate input vectors according to prescribed signal probability and activity. A set of so-far worst case input vectors is selected to form an initial gene pool Genetic algorithm is employed to generate the new generations of input vectors Worst case noise & corresponding input vectors are the goals Pre-characterization of Standard Cells Technology and design parameters available Standard cells are pre-characterized with SPCE to obtain drive capability and delay information A delay loo-up table is used for timing analysis Current waveforms are approximated as trapezoids based on the delay and drive capability of switching gates 9

10 Delay Model--Looup Table A delay looup table is tabulated for each standard gate based on SPCE simulation data Delay depends on capacitive load and input slope Linear interpolation is used if necessary nput slope Capacitive load Delay Output slope τs CL td τo (ps) (ff) (ps) (ps) Approximate Switching Current Waveforms with Trapezoid 10

11 Switching Current Waveforms & Timing nformation Switching Event Queue (Event-driven Simulator) Determine Delay & Switching current waveform Switching event D Cloc Cycle ( T ) Modeling P/G Networ P/G networ is modeled as pseudodistributed RLC networ (of tree topology) 11

12 Noise Calculation P = P P Zd( 3) Z d (3) d(3) VDD i3(t) R1 L1 C1 i1(t) R2 L2 C2 Z i2(t) di1 di3 di2 Vdd V Z = [ ir 1 1+ L1 ] + [ i3r 1+ L1 ] + [( R1 + R2 ) i2 + ( L1 + L2 ) ] dt dt dt Noise Feedbac & Data Postprocessing Noise bounce on P/G reduces the effective power supply, therefore, lowers the drive current and prevents the noise bounce from going worse Estimated data need to post-processed Assume triode region operation, noise feedbac is given as follows: V V ( 1 est noise act noise δ = ) = 2 δ β β V V dd = dd δ 12

13 Experimental Results Circuit P s No. Gate No. Pea Noise (Near End) Pea Noise (Far End) CPU Time (per input pattern) (mv) (mv) (s) C C C C C C C C C C C Experimental Results 13

14 Experimental Results Experimental Results (compared with SPCE) 14

15 Voltage Drop Correction Given a floorplan with switching activities information available for each module: Determine how much decap is required by each module to eep the supply noise below a specified upper limit Allocate white-space to each module to meet its decap budget Related issue Determine worst case power supply noise for each module in the floorplan Allocate the existing white space in the floorplan Power Supply Networ RLC Mesh :Current Source : VDD pin Lp VDD Rp VDD VDD VDD 15

16 Current Distribution in Power Supply Mesh :Connection point, VDD (1) :VDD pin Current contribution (3) Current flowing path (5) VDD (2) (6) Module A B C Current Distribution in Power Supply Networ Distribute switching current for each module in the power supply mesh Observation: Currents tend to flow along the leastimpedance paths Approximation: Consider only those paths with minimal impedance --shortest, second shortest, Z 1 j = = 2 + Z 2 Y j n Y i i = 1 L 2, + = n L = = j Z = n n 1, 2, K n 16

17 Decoupling Capacitance Budget Decap budget for each module can be determined based on its noise level nitial budget can be estimated as follows: Charge : Noise Decap : C Q ratio : ( ) ( ) τ ( ) = 0 ( t) dt θ = max(1, 1 = (1 ) Q θ ( ) V V / ( ) noise (lim) V noise ) (lim) noise, = 1,2,LM terations are performed if necessary until noise at each module in the floorplan is ept under certain limit Allocation of Decoupling Capacitance Decap needs to be placed in the vicinity of each target module Decap requires WS to manufacture on Use MOS capacitors Decap allocation is reduced to WS allocation Two-phase approach: Allocate the existing WS in the floorplan nsert additional WS into the floorplan if required 17

18 Allocation of Existing White Space A w2 WS B D w1 C E w3 Allocation of Existing WS-- Linear Programming (LP) Approach Objective: Maximize the utilization of available WS Existing WS can be allocated to neighboring modules using LP Notation: S : S : S ( j) x ( j) : : ws sum area of decap of allocated N : neighbors set allocated WS budget to of of mod WS WS j mod j from LP Approach: maximize WS st.. j N = H = 1 x ( j) S = x x ( j) ( j) 0, H = 1 j N S S, ( j), x ( j), = 1,2, L, H j, j= 1,2, L, M 18

19 nsert Additional WS into Floorplan f Necessary Update decap budget for each module after existing WS has been allocated f additional WS if required, insert WS into floorplan by extending it horizontally and vertically Two-phase procedure: insert WS band between rows based the decap budgets of the modules in the row insert WS band between columns based on the decap budgets of the modules in the column Moving Modules to nsert WS Original floorplan 0 A C 2 B D ExtY Moving modules in y+ direction A C B D WS band E G F E F G (a) (b) 19

20 Experimental Results Comparison of Decap Budgets (Ours vs Conventional Solution ) Circuit decap budget (nf) (our method) decap budget (nf) ( greedy solution ) Percentage (%) apte xerox hp ami ami playout Experimental Results for MCNC Benchmar Circuits Circuit Modules Existing WS (µm 2 ) (%) apte (1.6) xerox (5.5) hp (7.8) ami (21.3) ami (7.0) playout (6.6) decap Budget (nf) nacc. WS (µm 2 ) (%) Added WS (µm 2 ) (%) (0) (10.3) (0) (2.7) (3.5) (3.4) Est. Pea Noise (V) before Est. Pea Noise (V) after N/A (2.5) (0.9) (1.3) (4.0)

21 Floorplan of playout Before/After WS nsertion 21