Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design)

Transcription

1 Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design) Dr. Yingtao Jiang Department of Electrical and Computer Engineering University of Nevada Las Vegas Spring, 2006

2 Objectives Understand the importance of interconnects in VLSI systems Learn how interconnects scale Learn how interconnect delay and power are modeled Resistance Capacitance Inductance Learn how interconnect delay and power are optimized at various levels

3 Interconnect Impact on Chip

4 Wire Models All-inclusive model Capacitance-only

5 Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive

6 Nature of Interconnect Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II No of nets (Log Scale) S Local = S Technology Global Interconnect S Global = S Die Source: Intel ,000 10, ,000 Length (u)

7 Readings H. B. Bakoglu, Circuits interconnects and packaging for VLSI, Addison Wesley W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge Press J. M. Rabaey, Digital Integrated circuits : A design perspective, Prentice Hall A. Chandrakasan, W. J. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press

8 Components of VLSI system Logic Functional Block Router Logic Logic Gates Transistors Interconnects L2 Cache Cache Tags L2 Cache Power/ground and Clock Inter-block Signals Intra-block Signals Processor Core

9 Delay with technology scaling This figure is from the ITRS Roadmap on interconnects

10 Wire Delay

11 Wire Delay in the 35-nm Technology For the 35-nm technology generation using a copper conductor, a low- κ dielectric with κ=2, and a benchmark length L = 1.0 mm the interconnects RC response time is τ 250 ps. In comparison, the switching delay or latency of a minimum-geometry 35-nm generation MOSFET is τ d 2.5 ps.

12 Interconnect dimension trends in terms of IC generations These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001

13 Trends in some integrated circuit parameters Local wiring pitch (nm) Chip size at production (mm 2 ) Total interconnect length (m/cm 2 ) On-chip local clock (GHz) Number of metal levels Maximum power (W) Package pin-count (high-performance)

14 Rent s rule Rent s rule relates the I/O requirement to the number of gates as : N = K p p As technology scales number of gates in a given area is increasing. More routing is required as technology scales. N β g

15 Nature of the interconnect Local Interconnect Number of wires Donath Occupation prob. Measurement Global Interconnect Wire length These figures are derived from Digital integrated circuit a design perspective, J. Rabaey Prentice Hall and a tutorial in SLIP by Dirk Stroobandt respectively

16 Interconnect Topologies A[0] Multi-sink A[1] A[63]... Bus or Routing Channel Grid Multi-source

17 Modern interconnect These figures are derived from Digital integrated circuit a design perspective, J. Rabaey Prentice Hall and ITRS roadmap on interconnect respectively

18 Multiple Interconnect Layers

19 Interconnects are critical Chip Area Increasing. Average physical length increasing. Electrical length of interconnects increasing faster than physical length. Number of Interconnects increasing. Longer and more wires imply more delay (RC) and power ( C L V 2 DD f )

20 Interconnect Solutions Design Methods - Timing Driven Floorplanning Devices - Improved I dsat, Dual V t Materials - Copper Interconnect, Low K Dielectric Geometries - Tall wires, Layers of metals, Shields Signaling Methods - Differential, Limited Swing Novel Methods - Wireless communication, Optical Interconnects

21 VLSI Design Cycle Chip Specs Partitioning Floorplan RTL Synthesis Timing Analysis Timing met Layout Extraction Timing Analysis Timing met Chip Tape out

22 Interconnect Focused Floorplanning Architectural Performance Sensitivity to Interconnect Delay Early Floorplanning Impact of New Circuit Techniques Interconnect-aware Architecture Design

23 Wire Models Why do we need models? Models simplify analysis and simulation. Why model wires? Estimate the delay due to wire. Check for signal integrity and reliability. What are the implications of a wrong model? Delay estimates can be wrong leading to slow or fast failures. Might lead to over or under driving leading to power dissipation and reliability concerns.

24 Ideal Model Wires are lines on schematics having no electrical effect. A voltage change at one end appears at its other end without any delay i.e. wire is a equipotential region. Ideal model simplistic Most wires connect local gates hence are short Ideal model might be ok For long i.e. global interconnects ideal model is absolutely wrong.

25 Early Models Wire width feature size Older technology had wide wires More cross-section area implies less resistance and more capacitance. Model wire only with capacitance H W L

26 However With scaling, width of wire reduced. Resistance of the wire no longer negligible. Wire not very long and a lumped RC is good enough approximation. L H W

27 Interconnect Resistance H L R = ρl HW W Ohm s Law: Resistance of wire wire length (L) and 1/ cross-section(hw) ρ (resistivity) is the property of the material.

28 Sheet Resistance Wire height (H) is constant for a technology. Sheet resistance (R q ) is constant for each metal layer. Calculation of wire resistance is easy : multiply R q by L/W R with R q = = R q ρ H L W

29 Interconnect Resistance

30 Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length

31 Polycide Gate Mosfet Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

32 Sheet Resistance

33 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

34 Interconnect Capacitance Capacitance of a wire = f (Shape, Distance to surrounding wires, Distance to the substrate ) Estimating Capacitance is a non-trivial task subject of active research. To get an accurate estimate electric field solvers (2D or 3D) should be used. Solving fields is slow and will take ages for estimating capacitance of the whole chip. Various assumptions and approximations used to get quick estimates.

35 Area Capacitance Current W L H t di Dielectric Electric Fields Substrate C int = ε di t di WL

36 Permittivity

37 Fringing Capacitance Fringing Fields H w Conductor + C wire = C pp + C fringe = 2πε log( t / di di H ) + wε t di di w W-H/2

38 Detailed Picture Is this much of detail required How to compute this?

39 Impact of Interwire Capacitance (from [Bakoglu89])

40 Wiring Capacitances (0.25 µm CMOS)

41 Orthogonal Capacitance Orthogonal capacitance is usually small May be necessary to compute sometimes for signal integrity issues.

42 Capacitance Crosstalk V DD Capacitive coupling introduces crosstalk. In 1 In 2 In 3 φ φ PDN C XY X C X Y 5V OV Crosstalk slows down signals to static gates, can cause hard errors in storage nodes. Crosstalk can be controlled by methodological and optimization techniques. 5x5 µm Overlap: 0.35 V Interference

43 Coupling and Crosstalk Crosstalk current depends on capacitance, voltage ramp. i c w1 w2 t C c

44 Crosstalk Analysis Assume worst-case voltage swings, signal slopes. Measure coupling capacitance based on geometrical alignment/overlap. Some nodes are particularly sensitive to crosstalk: dynamic; asynchronous.

45 Coupling Situations bus[0] sig1 a x r better bus[1] bus[2] worse

46 Layer-to-layer Coupling Long parallel runs on adjacent layers are also bad. SiO 2 siga bus[0]

47 Methodological Solutions Add ground wires between signal wires: coupling to V SS, a stable signal, dominates; can use V SS to distribute power, so long as power line is relatively stable. Extreme case add ground plane. Costs an entire layer, may be overkill.

48 Ground Wires V SS sig1 V SS sig2 V SS

49 Crosstalk and Signal Routing Can route wires to minimize required adjacency regions. Take advantage of natural holes in routing areas to decouple signals. Minimizes need for ground signals.

50 Crosstalk routing example Channel:

51 Assumptions Take into account coupling only to wires in adjacent tracks. Ignore coupling of vertical wires. Assume that coupling/crosstalk is proportional to adjacency length.

52 Bad routing

53 Good routing

54 Multi-level Interconnection

55 The Lumped Model V out Driver c wi re R driver V out V in C lumped

56 Versions of Lumped Model A driver doesn t see the total R or C of the wire. Versions of lumped model were used as good approximations. L model T model π model

57 Importance of Resistance Delay of wire to the resistance of the wire. Resistance means ohmic (IR) drop along the wire, reduces noise margin. IR drop a significant problem in the power lines where current density if high. Keep wires short, to reduce resistance. Contact resistance makes them vulnerable to electromigration.

58 How to Reduce Resistance? Materials with low resistivity (Cu). Reduce wire length not always possible. Increase width increases area and capacitance. Increase height increases fringe capacitance. Provide bigger contacts, use less vias. Use metal instead of polysilicon even for short distance routing. Use silicide coating to reduce polysilicon resistance.

59 Accurate Estimate of Cap Accurate estimate of capacitance can be done for any geometry by using field solvers. Electric fields can be solved in 2D or 3D to accurately estimate the capacitance. Example field solver FASTCAP Output usually being a capacitance matrix.

60 Estimate C Early in Design Cycle Imperative to estimate wire delay. Electric fields attenuate very fast. To calculate capacitance consider only near neighbors (both axes) A table of capacitance to ground per unit length for a given width can be created. Capacitance with horizontal neighbors depends on wire spacing.

61 Importance of Capacitance Delay of the wire is proportional to the capacitance charged. More capacitance means more dynamic power. Capacitance an increasing source of noise (coupling). Coupling make delay estimation hard.

62 How to Reduce Capacitance? Use low k dielectric which reduces permittivity and hence the capacitance. Increase the spacing between the wires (not always possible). Separate the two signals with a power or ground line (acting as shield). Use wire with minimum width wherever possible. (Increases resistance!)

63 Distributed model Wire can be modeled as a distributed RC line. As the number of elements increase distributed model becomes more accurate. For practical purposes wire-models with 5-10 elements are used to model the wire.

64 The Distributed RC-line

65 Step-response of RC Wire as a Function of Time and Space x= L/10 voltage (V) x = L/4 x = L/2 x= L time (nsec)

66 RC-Models

67 Driving an RC-line R s (r w,c w,l) V out V in

68 Reducing RC-delay Repeater

69 Delay in distributed RC line Elmore analyzed the distributed model and came up with the figures for delay. V in R 1 R R i-1 i-1 R i i R N-1 N-1 R N N V out C 1 C 2 C i-1 C i C N-1 C N τ N = N i= 1 R i N j= i C j = N i= 1 C i i j= 1 R j Elmore derived this equation in 1948 way before VLSI!!!

70 Elmore Delay First order time constant at node is a sum of RC components. All the upstream resistances are taken into account. Thus each node contributes to the delay. Amount of contribution is the product of the cap at the node and the amount of resistance from source to the node.

71 Generalized Elmore delay Rubinstein, Pinfield and Horowitz generalized Elmore delay This figure is derived from Digital integrated circuit a design perspective, J. Rabaey Prentice Hall

72 Inductance Early models didn t include inductance. For VDSM Designs it cannot be ignored. Distributed RC model no longer accurate. Distributed RLC model should be used. Difficult to analyze second order differential equations!!

73 LC coupling, self L and return R These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001

74 Inductive noise vs. line length This figure is derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001

75 Impact of signal returns on farend These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001

76 Inductive Effects in Integrated Circuits Coaxial Cable Triplate Strip Line MicroStrip Wire above Ground Plane

77 Decoupling Capacitors + Board Wiring Bonding Wire SUPPLY C d CHIP - Decoupling Capacitor

78 The Transmission Line V in r l r l r l x r l V out g c g c g c g c

79 Lossless Transmission Line - Parameters speed of light in vacuum

80 Wave Propagation Speed

81 Wave Reflection for Different Terminations

82 Transmission Line Response (R L = ) V V Dest V Source R S = 5Z 0 (a) V R S = Z 0 (b) V R S = Z 0 / t (in t lightf ) (c)

83 Lattice Diagram V Source V Dest V V V V t V V V V... L/ν

84 ECL Gate Line Response V cc V cc V cc V cc R C R C R C V in V ref L=2cm V EE R B I EE Z 0 = 100Ω VEE R B I EE V EE (a) k -1.0 Vout t (nsec)

85 Output Buffer Model V DD L = 10nH Clamping Diodes V DD V in L = 5nH Z 0 = 100 V out C L = 5pF C L R L L = 10nH (a)

86 Output Buffer - Response V in Clamped C L = 5pF R L = 10kΩ Vout 0.0 Unclamped C L = 5pF R L = 100Ω Vout (b) C L = 25pF R L = 100Ω Vout t (nsec)

87 When to Consider Transmission Line Effects?

88 RI Introduced Noise V DD I φ pre R V DD - V X V I R V

89 Power and Ground Distribution V DD Logic GND (a) Finger-shaped network V DD GND GND Logic V DD (b) Network with multiple supply pins Must size wires to be able to handle current requires designing topology of V DD /V SS networks. Want to keep power network in metal requires designing planar wiring.

90 Power distribution V DD V SS Interdigitated power and ground lines

91 Power tree design Each branch must be able to supply required current to all of its subsidiary branches: I x = b x I b Trees are interdigitated to supply both sides of power supply.

92 Planar power/ground routing theorem Draw a dividing line through each cell such that all V DD terminals are on one side and all V SS terminals on the other. If floorplan places all cells with V DD on same side, there exists a routing for both V DD and V SS which does not require them to cross. V SS V DD cell V SS V DD

93 Planar routing theorem example

94 Power supply noise Variations in power supply voltage manifest themselves as noise into the logic gates. Power supply wiring resistance creates voltage variations with current surges. Voltage drops on power lines depend on dynamic behavior of circuit.

95 Tackling power supply noise Must measure current required by each block at varying times. May need to redesign power/ground network to reduce resistance at high current loads. Worst case, may have to move some activity to another clock cycle to reduce peak current.

96 Clock distribution Goals: deliver clock to all memory elements with acceptable skew; deliver clock edges with acceptable sharpness. Clocking network design is one of the greatest challenges in the design of a large chip.

97 Clock delay varies with position

98 H-tree

99 Clock distribution tree Clocks are generally distributed via wiring trees. Want to use low-resistance interconnect to minimize delay. Use multiple drivers to distribute driver requirements use optimal sizing principles to design buffers. Clock lines can create significant crosstalk.

100 Clock distribution tree example