Low Power Design for Systems on a Chip. Tutorial Outline

Transcription

1 Low Power Design for Systems on a Chip Mary Jane Irwin Dept of CSE Penn State University ( Low Power Design for SoCs ASIC Tutorial Intro.1 Tutorial Outline Introduction and motivation Processor core power reduction techniques Memory system power reduction techniques SoC clock power reduction techniques SoC bus power reduction techniques Future challenges Low Power Design for SoCs ASIC Tutorial Intro.2 1

2 Power Power is the rate at which energy is delivered or exchanged» electrical energy is converted to heat energy during operation Power Dissipation - rate at which energy is taken from the source (V dd ) and converted into heat Low Power Design for SoCs ASIC Tutorial Intro.3 Why Power Matters Packaging costs; cooling costs Power supply rail design Digital noise immunity Battery life (in portable systems) Environmental concerns» Office equipment accounted for 5% of total US commercial energy usage in 1993» Energy Star compliant systems Low Power Design for SoCs ASIC Tutorial Intro.4 2

3 Technology Directions: SIA Roadmap Year Feature size (nm) Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) #pads/chip Clock (MHz) Chip size (mm 2 ) Wiring levels Power supply (V) High-perf pow (W) Battery pow (W) Low Power Design for SoCs ASIC Tutorial Intro.5 Chip Power Densities W/cm Hot plate Process (microns) From Borkar,, 1999 Low Power Design for SoCs ASIC Tutorial Intro.6 3

4 Nominal Capacity (Watt-hours / lb) Battery Technology Improvements BATTERY (40+ lbs) 50 Rechargable Lithium 40 Ni-Metal Hydride Nickel-Cadium Year Expected battery lifetime increase over next 5 years: 30-40% Low Power Design for SoCs ASIC Tutorial Intro.7 Intro.7 From Rabaey, Rabaey, 1995 Where Does Power Go in CMOS? l Dynamic Power Consumption» charging and discharging capacitors l Short Circuit Currents» short circuit path between supply rails during switching l Leakage Current» leaking diodes and transistors l Static Currents» design styles such as pseudo NMOS Low Power Design for SoCs ASIC Tutorial Intro.8 Intro.8 4

5 CMOS Gate Energy/Power Equations E = 1/2 C L V dd2 + (t r + t f )/2 V dd I peak + V dd I leakage P = C L V dd2 f + (t r + t f )/2 V dd I peak f + V dd I leakage Low Power Design for SoCs ASIC Tutorial Intro.9 Dynamic Power Consumption Vdd Vin Vout C L Energy/transition = C L P 0 1 * Vdd 2 Power = Energy/transition * transition rate = C L P 0 1 * Vdd 2 * f Not a function of transistor sizes! Data dependent - a function of switching activity! Low Power Design for SoCs ASIC Tutorial Intro.10 5

6 Short Circuit Currents Determinates (t r + t f )/2 V dd I peak Duration and slope of the input signal I-V curves of the P and N transistors which depend on their sizes, process technology, temperature, etc. Output loading capacitance Low Power Design for SoCs ASIC Tutorial Intro.11 Short-Circuit Current Variation with Input Signal Slope V 1ns 2ns 4ns I(sc) t 1ns 2ns 4ns t Low Power Design for SoCs ASIC Tutorial Intro.12 6

7 Leakage Currents Vdd V dd I leakage Vout Drain junction leakage Sub-threshold current Sub-threshold current is the dominant factor. Increases exponentially with temperature! Low Power Design for SoCs ASIC Tutorial Intro.13 Sub-Threshold in MOS I D V T =0.2 V T =0.6 V GS Lower bound on threshold voltage to prevent leakage Low Power Design for SoCs ASIC Tutorial Intro.14 7

8 Glitching in Static CMOS A B X Z ABC X Z Unit Delay Low Power Design for SoCs ASIC Tutorial Intro.15 Glitching in an RCA C in Add0 Add1 Add2 Add14 Add15 S0 S1 S2 S14 S15 Sum Output Voltage, Volts Cin S1 S Time, ns S15 From Rabaey,, 1995 Low Power Design for SoCs ASIC Tutorial Intro.16 8

9 Basic Principles of Low Power Design P = C L V dd2 f + (t r + t f )/2 V dd I peak f + V dd I leakage Reduce switching (supply) voltage» quadratic effect -> dramatic savings» negative effect on performance Reduce capacitance Reduce switching frequency Reduce glitching Reduce leakage and static currents Low Power Design for SoCs ASIC Tutorial Intro.17 Reducing V dd Lowers Energy NORMALIZED POWER-DELAY PRODUCT quadratic dependence 51 stage ring oscillator 8-bit adder Vdd (volts) 2 P x t d = E t = C L * V dd E(Vdd=2) (C L) * (2) 2 = E (CL) * (5) 2 (Vdd=5) E(Vdd=2) 0.16 E(Vdd =5) Strong function of voltage (V 2 dependence). Relatively independent of logic function and style. Power Delay Product Improves with lowering V DD. From Rabaey,, 1995 Low Power Design for SoCs ASIC Tutorial Intro.18 9

10 Reducing V dd Increases Delay NORMALIZED DELAY multiplier clock generator ring oscillator adder adder (SPICE) 2.0µm technology microcoded DSP chip V dd (volts) T d = T d(vdd=5) C L * V dd I I ~ (V dd - V t ) 2 T d(vdd=2) = (2) * (5-0.7) 2 4 (5) * (2-0.7) 2 Relatively independent of logic function and style. From Rabaey,, 1995 Low Power Design for SoCs ASIC Tutorial Intro.19 Figures of Merit Power consumption in Watts» packaging consideration and cooling requirements» system power supply Peak power» power ground wiring designs» signal noise margin and reliability analysis Power (energy) efficiency of a circuit in Joules» rate at which energy is consumed over time» energy dissipation per clock cycle» lower energy number means less power to perform a computation at the same frequency Energy-delay or power-delay product (PDP) Low Power Design for SoCs ASIC Tutorial Intro.20 10

11 Design Levels Abstraction Power Analysis Analysis Level Savings Resources Accuracy Most Least Worst Algorithm Software/system Architecture Functional unit Gate Circuit Least Most Best Low Power Design for SoCs ASIC Tutorial Intro.21 Analysis Techniques Simulation techniques» characterization - using lower level analysis tools to construct higher level models very computationally intensive can be very accurate gives cycle accurate numbers Probabilistic techniques» signals are viewed as random zero-one processes with certain statistical characteristics computationally efficient accuracy depends on input statistics assumptions gives average value for a sequence of cycles Low Power Design for SoCs ASIC Tutorial Intro.22 11

12 Key References Borkar, Design Challenges of Technology Scaling, IEEE Micro, pp , Aug Chandrakasan, Broderson, Low Power Digital CMOS Design, KAP, Najm, A survey of power estimation techniques in VLSI circuits, IEEE Trans. on VLSI Systems, 2(4): , Pedram, Power minimization in IC design, ACM TODAES, 1(1):3-56, Proceedings of ACM/IEEE Symposium on Low Power Electronics and Design (SLPED), Rabaey, Digital Integrated Circuits, Prentice-Hall, Rabaey, Pedram, Low Power Design Methodologies, KAP, SIA Roadmap, notes.sematech.org/ntrs/pubintrs.nsf Tiwari, Reducing power in high-performance microprocessors, Proc. of DAC, pp , Yeap, Practical Low Power Digital VLSI Design, KAP, Low Power Design for SoCs ASIC Tutorial Intro.23 12