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1 1061 Area Leakage Power and delay Optimization BY Switched High V TH Logic UDAY PANWAR 1, KAVITA KHARE 2 12 Department of Electronics and Communication Engineering, MANIT, Bhopal 1 panwaruday1@gmail.com, 2 kavita_khare1@yahoo.co.in ABSTRACT As technology scales, leakage power became the major constraint in VLSI CMOS circuit design. A new approach based on convectional gate replacement is proposed. According to this technique gate is replaced which is having Worst Leakage State (WLS) at a particular input vector for the given circuit. The proposed approach is more effective for the circuits having large logic depth. Primary concern is the leakage reduction when circuit operates in active mode of operation; the purpose is to care on run time leakage saving technique of integrated Circuit. Proposed algorithm provides the optimized way to control leakage as well as area and delay during runtime of the device. Here a PMOS transistor with high threshold voltage (V TH ) used as a switched logic which reduces the leakage during standby mode of the device and maintains the logic behavior during active mode with very less delay and area. Switched high V TH approach is applied on the ISCAS 85 circuit C17 and achieved leakage power reduction of 40.27% with only 1.7% delay increased as compared to the conventional input vector control technique. Here also a comparative analysis is given based on number of gate replacement and this approach required only 16.7 % gate replacement which is quite low. Keywords: IVC, Subthreshold Leakage, Minimum Leakage vector (MLV), Gate replacement technique [1] INTRODUCTION To achieve higher chip density and operating speed with lowering the leakage power dissipation, CMOS device has been scaled. According to Moore s law doubling the transistor with the same chip in every 2 year. Leakage [1] power has becoming dominating source among all the sources of power dissipation of a CMOS IC Deep Sub Micron (DSM) process technology nodes (65nm and below) because it has increased to 30-50% of the total IC power consumption. As frequency increases the switching power dissipation (P dy ) is increased. To control switching power dissipation supply voltage (V DD ) has been reduced. But it was affected the circuit above 90nm technology where Pdy was the primary source of total power dissipation of the chip. In DSM the subthreshold and gate oxide leakage power dissipation became the dominating source of power dissipation among all the sources of power dissipation of CMOS IC. It can be seen through Figure 1 which shows active and standby leakage percentage of a microprocessor chip by Intel [15]. In order to maintain the performance of the chip and high driving capability with lower supply voltage the V TH is reduced. However, the threshold voltage scaling results in the substantial increase of the subthreshold leakage current [2]. Figure 1. active and standby leakage percentage of a microprocessor chip by Intel Leakage power is primarily the result of undesirable channel current from drain to source of the transistor when it is in the cut off region. This subthreshold leakage power is strongly influenced by scaling of the transistor threshold voltage V TH (the voltage applied to the gate terminal that turns on the transistor). It is a substantial problem in portable electronic gadgets such as Tablet PC s Notebook etc. the leakage power can give approximately 42% of the overall power dissipation in CMOS VLSI circuit design at DSM technology [6]. Some techniques have been evaluated on the basis of their mode of operation and responsible for minimizing the leakage of the chip. Dual threshold voltage (DVT) [7] process uses two kind of threshold voltage. High V TH for the paths which creates larger delay and for remaining paths low V TH transistor is used through this way leakage is highly reduce. Multiple threshold CMOS (MTCMOS) [7-8] or power gating technique uses a high V TH transistor connected in between VDD and PULL UP device and PULL DOWN device and ground. The purpose of this kind of arrangement of new extra transistor is to cut off the circuit from the power rail and ground during standby mode, this extra connected transistor is termed as sleep transistor, another operative method known as Input Vector Control (IVC) [3-5], is used during active mode of operation of the device. It exploits the stacking result of the circuit where more off transistor in series reduced the leakage. But drawback of this technique is to

2 1062 control over primary inputs of the device. With the help of IVC technique finds the IVC of the device and after applying gate replacement technique at the given input pattern more leakage is reduces as compare to the IVC alone. 2. RELATED WORK Several approaches have been projected to develop MLV; the most of these are founded on heuristics, so their results are not prime. In [9], an Integer Linear Programming (ILP) is given to calculate an MLV. A suitable linear moderation to offer a lower bound on the integer optimum and then employ a technique called randomized rounding to round the solution to the linear moderation, which is typically fractional, to an integer solution. The problem is expressed as ILP in two dissimilar techniques. One scheme consists of relaxing the ILP formulation to obtain a lower bound on the minimum leakage power that is dissipated by the circuit. The linear moderation of the first ILP formulation is shown hypothetically to be of meager quality, while the moderation to the second ILP origination is shown to work considerable in practice. ILP is not prime and needs large runtime. In [10], another heuristic based method to find the MLV is evaluated. Here considered only that part of the chip is in standby mode which is a general method in low power design. Here a new technique is proposed that can be used during logic design to moderate the leakage power of CMOS circuits that use clock gating to reduce the switching power dissipation. Using negligible extra circuitry, it adapts the original logic design to force into a low leakage state during the standby mode of operation. To find MLV, they have developed a well-organized algorithm that determines a noble input vector using a sampling of random vectors. The size of sampling is determined a priori user-supplied quality measures. They have demonstrated this method on the ISCAS-89 benchmark circuits and shown leakage power reduction of up to 54%. This algorithm is meager and not ideal. In [11], a genetic algorithm was suggested to overcome the problem of finding MLV Genetic algorithm has an exponential solution space. Here chromosomes are characterized by the input vectors, and calculation method of the leakage current represents the fitness function. The algorithm picks the parents randomly to make crossover between them to produce the new children. At the end of the method, the parent with the least leakage current is chosen as the MLV. It is not optimal and need exponential space complexity and large runtime. In [12] it is proposed a fast algorithm having the concept of controllability, which is extensively used for error tolerance finding. Here the controllability of every gate in the circuit is designed. The algorithm rejects the minimum cost nodes. The final state is attained by excluding all the nodes in the list. The simulation results showed that the results vectors are among 5% of the best vector acquired from 100K random vectors, but it requires a large run time. Graph based algorithms [13], Presents for approximating the maximum leakage power. These algorithm does not finding the MLV, it is pattern-independent and do not require simulation. In its place the circuit arrangement and the logic behavior of the instance in the circuit are used to make a constraint graph. The problem of approximating the maximum leakage power is then converted to an optimization problem on the constraints graph. Efficient algorithms used to calculate the maximum leakage power and compared with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuit. 3. PROPOSED ALGORITHM To achieve the maximum reduction of leakage power for CMOS VLSI digital circuit designing an integrated approach is proposed. Proposed approach utilizes the qualities of Input Vector Control and gate replacement techniques. The algorithm based on 2 ideologies. (a) Transistors are in OFF state and (b) The potential difference between drain to source of that transistor (i.e. V DS ) should be maximum. Here it is equals to V DD. Firstly MLV of the given circuit is found using IVC technique and shifts the logic circuit to its minimum leakage level. After that an algorithms applied on the circuit which finds the dominant gate or gate having WLS. Those gates are replaced by the high V TH transistors which are at their WLS. Now leakage and delay is estimated. If the both values is considerable than stop the process otherwise no need to any replacement. Above condition checks for every path of the graph and result is the sum of the entire OFF transistor in every path of the graph for a specific input combination. And the input vector which gives least leakage power sets as MLV of the given logic cell. Figure 2 gives the pseudo steps for proposed approach. 3.1 Pseudo code for the proposed algorithm Input: {L 1, L 2, L 3 L n }-logics of the circuit in topological order. {V 1, V2, V3 V n } -Variation of Cell Library of some basic cell for replacement Output: An optimized logic circuit with less leakage and delay with similar behaviour. High V TH gate replacement steps:- i. Read the Netlist of a circuit and arrange it in a graph T 1.

3 1063 ii. Initialize the input pattern {I 1, I 2, I 3.I k } as {0,0,0, 0} iii. Calculate the leakage at each path of the T1 iv. Repeat the process for every input pattern or half of the pattern. v. Select the input pattern as a MLV at which it gets the minimum leakage. vi. Set the MLV as a primary input. vii. For each gate {L 1, L 2, L 3 L n } Check the dominant gate at MLV. viii. Replace it with High V TH switched logic variation of that gate from {V 1, V2, V3 V n }. ix. Check leakage and delay for the replacement of gates. x. If replaced gate is reduces the leakage with slightly less delay then it is selecting. Otherwise go for next replacement of the circuit. xi. Once gate is processed then go to (vii). xii. Process stop. Figure 2. Gives the pseudo steps for proposed approach 3.2 Cell Variation Representation for Switched High V TH Logic VDD High VTH PMOS NAND Logic GND Figure 3. Switched High V TH PMOS Logic 4. CIRCUIT DIAGRAM For the analysis C17 ISCAS- 85 benchmark circuit is used which shows in Figure 4. It consists of 6 NAND cell. Also Schematic vies and behaviour waveform is presented in Figure 5, & 6 respectively. Figure 4. C17- ISCAS 85 benchmark Figure 5. C17 Schematic view by Cadence Virtuoso

4 1064 Figure 6. Waveform of C17 Benchmark circuit 5. SIMULATION RESULT The proposed approach is simulated on HSPICE and C17 ISCAS 85 benchmark circuit taking for analysis. Analysis gives the WLS and MLV of the given circuit first and then it finds the suitable gate for replacement. It is used BPTM 45nm model library for circuit. For given circuit WLS condition got at and MLV at Figure 7 gives the comparison of number of gate replacement for increasing the reduction of leakage power. Figure 7. Gives the comparison of number of gate replacement for increasing the reduction of leakage power of C17 Benchmark ISCAS with all input pattern Here another graph is presented in Figure 8 for the MLV of the device with every gate replacement. It can be seen from here that if gate replacement is higher than it increases the area as well as delay of the circuit for better result we have to keep trade of between all parameters. Figure 8. comparative analysis of area power and delay with gate replacement

5 1065 CONCLUSIONS The proposed Switched High V TH algorithm gives an effective explanation for finding MLV and replace its appropriate logic gate without increases the number of replacement, which directly increases the area of the circuit. It can be seen from the Figure 8 for higher performance application proposed approach of high VTH gives optimum result. It can be select any one of them as per designer requirement. Through this algorithm leakage power reduction is achieved of % as compared to the conventional leakage power which requires only single gate is replaced, only 1.75 % of delay is increased of C17 circuit which is quite significant for practical purposes. REFERENCES [1].Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits, Proceeding of the IEEE, Vol. 91, no. 2, FEBRUARY 2003 PP [2].V. De and S. Borkar, Technology and Design Challenges for Low Power and High Performance, in Proceedings of International Symposium on Low Power Electronics and Design, pp , August [3].A. Abdollahi, F. Fallah, and M. Pedram, Leakage current reduction in CMOS VLSI circuits by input vector control, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp , Feb [4].Lei Cheng, Liang Deng, Deming Chen, and Martin D.F. Wong, A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction, In DAC, 2006, pp [5].Lin Yuan and Gang Qu A Combined Gate Replacement and input vector control approach for leakage current reduction IEEE transactions on very large scale system,vol. 14 no. 2, February [6]. J. Kao, S. Narendra, and A. Chandrakasan, Subthreshold leakage modelling and reduction techniques, in Proc. ICCAD, 2002, pp [7].M.C.Johnson, D.Somasekhar and K.Roy, Leakage Control with efficient use of transistor stacks In single threshold CMOS, ACM,/ IEEE Design Automation Conference 1999, pp [8].B.S. Deepaksubramanyan, Adrian Nunez, Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits, Proceeding of the 13th NASA Symposium, Post Falls Idaho, June 5-6, 2007,pp [9].S. Naidu & E. Jacobs, Minimizing stand-by leakage power in staticcmos circuits, Proc. DATE, 2001, pp [10]. Halter, and F. Najm, A Gate-Level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits, IEEE Custom Integrated Circuits Conference,1997, pp [11]. Z. Chen, M. Johnson, L. Wei, and K. Roy, Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks, International Symposium on Low Power Electronics and Design,1998, pp [12]. R. M. Rao, F. Liu, J. L. Burns, and R. B. Brown, A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits, in Proc. ICCAD, 2003, pp [13]. Bobba, S. and Hajj, I., Maximum Leakage Power Estimation for CMOS Circuits, Proc. of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, pp [14]. Nikhil Jayakumar, Sunil P Khatri, An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification Proceedings of the conference on Design, automation and test in Europe, Pages [15].