SUBTHRESHOLD CIRCUIT DESIGN FOR HIGH PERFORMANCE

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1 SUBTHRESHOLD CIRCUIT DESIGN FOR HIGH PERFORMANCE K. VIKRANTH REDDY 1, M. MURALI KRISHNA 2, K. LAL KISHORE 3 1 M.Tech. Student, Department of ECE, GITAM University, Visakhapatnam, INDIA 2 Assistant Professor, Department of ECE, GITAM University, Visakhapatnam, INDIA 3 Vice Chancellor, JNT University, Anantapur, INDIA 1 vikranth23791@gmail.com, 2 madugulamk@gmail.com 970 ABSTRACT In modern technology we want the digital circuits to consume less power and to operate at high speeds. In order to achieve this goal the devices are being operated in subthreshold region in order to reduce the energy consumption at a cost of reduced speed. In modern nanometer technology the threshold voltage will be lower than expected at narrow widths due to inverse narrow width effect. Due to this the subthreshold current is higher than expected at lower width. So we can replace a minimum width transistor and hence speed of the circuit can be improved. Similarly body biasing technique is used for altering the threshold voltage of mosfet and hence speed of the circuits can be increased. A ring oscillator using the above i.e. parallel stacking and body biasing is designed for high performance for application such as synchronizing computation in a digital system, timing the sampling in a data converter, carrier synthesis and LO in RF systems, etc. Finally a simple stream cipher which is used for data encryption and decryption is designed using proposed technique. Circuits are designed in gpdk 45nm technology using Cadence EDA tool. Keywords: Trench Isolation, Inverse Narrow Width Effect, Parallel Stacking, Body biasing, Stream cipher [1] INTRODUCTION Digital circuits operating in the sub-threshold region benefit from very low power consumption at the cost of speed. In the subthreshold region supply voltage (V dd ) less than the threshold voltage (V th ) of the transistor in such a technique the subthreshold leakage current of the device is used for necessary computation [1]. This result in high trans-conductance gain of the devices (thereby providing near ideal voltage transfer characteristics of the logic gates) and reduced gate input capacitance. Its impact on system design is an exponential reduction of power at the cost of reduced performance. There are various methods implemented to overcome this situation (to increase speed of the circuits). One of them is parallel stacking technique [2].In modern nanometer technologies the threshold voltage is lower at narrower widths due to the inverse-narrow-width effect [3]. the sub-threshold current may be higher at these narrow widths. So the performance can be improved (more current is produced) by replacing the large, single transistor with parallel transistors all sized at the sub-threshold optimum width. These optimum widths vary depending on the technology. Body biasing technique is used for altering the threshold voltage of mosfet and hence speed of the circuits can be increased or decreased. Forward biasing reduces the threshold voltages and thus increases the on currents of device. Reverse biasing raises the threshold voltages and thus reduce the subthreshold currents and saves power in standby mode. 2. TYPES OF ISOLATION There are different types of isolation like locos isolation (Older CMOS technologies and non-mos technologies commonly use locos isolation) and shallow trench isolation ( it is used in modern nanotechnology MOSFETs). Each of them has their own impact on threshold voltage variation. (a) (b) (c) Fig1. Three types of device structures and associated inversion depletion layer. (a)large-geometry MOSFET. (b) LOCOS gate MOSFET. (c) Trench isolated MOSFET [4] 2.1. Effect Of Locos Isolation:- Local Oxidation of Silicon (LOCOS) is the traditional isolation technique. In case of local oxide isolation (LOCOS) gate MOSFET, gate-induced depletion region to spreads outside the defined channel width as shown in Fig1.(b). This results in an increase of the total depletion charge in the bulk region above its expected value [4]

2 971 Where V th = V fb + Φ s + Q B C ox V fb is the flat-band voltage. φ s is the surface potential. C ox is the capacitance across the oxide. Q B is the depletion charge in the bulk. Due to narrow-width effect Q B increases by Q B as shown in Fig1.(b). This effect becomes more when channel width decreases, This results in increase of threshold voltage due to narrow-channel effect.[4] 2.2. Effect Of Trench Isolation:- Shallow trench isolation (STI) is an integrated circuit feature which prevents electrical leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250nm and smaller. In the case of trench isolation devices, depletion layer cannot spread under the oxide isolation [Fig1(c)]. The overall gate capacitance (C T ) includes the sidewall capacitance (C F ) due to overlap of the gate with the isolation oxide. This increases the overall gate capacitance. Overall gate capacitance increases and is given by C T = C ox W + 2C F,. Hence, the overall V th reduces due to inverse narrow width effect [5][6] as shown. Fig.2 Threshold voltage vs width for PMOS transistor in 45nm But in case of buried channel trench isolated PMOS anomalous behavior [6] is shown where reduction of the width first decreases the threshold voltage until the width is 0.4 m. The width reduction below 0.4 m causes a sharp increase in Vth as shown Fig3. Variation of threshold voltage with gate width in the case of trench isolated buried channel P-MOSFET in 45nm In general when width of the transistor decreases we expect its current carrying capability also to decrease as shown Fig4. Current vs width for PMOS transistor in 90nm But transistors in modern nanometer CMOS technologies usually exhibit inverse narrow width effect when operating in the subthreshold region, this phenomenon results in higher than expected current at smaller widths as shown

3 972 Fig5. Current vs width for PMOS transistor in 45nm So from Fig5 we can see that current at lower widths is more than expected. Hence if we replace a transistor of width 2W with two parallel transistors of width W then overall current produced will be more and hence the speed of the circuit can be improved. Where W = minimum width of the MOSFET where we are getting more current than expected (if we consider same Fig3 plot for a 90nm technology then we will find that the curve between current and width will be linear. If we use this technique there won t be any difference rather it leads to area overhead. So this technique is best suited for modern nanometer technologies)in a CMOS circuit parallel stacking can be done only to PMOS or only NMOS or both NMOS and PMOS transistors the those configurations are called P-PTS, N-PTS, PN-PTS respectively Optimum With Of A Transistor At a given width we want the MOSFET to carry more current so that the propagation delay gets decreased. When the width of the transistors is increased or decreased the capacitance associated with it changes proportionally. So the delay can be minimized by increasing the (I/C) ratio. So we need to find out the width of the transistor where this ratio will be high. In 45nm technology the optimum widths of NMOS and PMOS are found to be 120nm.The optimum with value gets changed depending on the technology used. As discussed earlier in case of 90nm technology there is no inverse narrow width effect so the optimum width may varies. Fig6. Current-to-capacitance ratio against width for PMOS transistor in 45 nm Fig7. Layout comparison of nand gate using without and with parallel stacking technique From above comparison we can clearly observe area of the circuits increases using parallel stacking technique. But delay of the circuits gets improved and this method can be used in both above and below threshold region of operation. 3. BODY BIASING TECHNIQUE Body biasing techniques have been used to alter the MOS threshold voltage in order to either increase the speed or reduce leakage. Forward biasing reduces the threshold voltages and thus increases the on currents of device. Reverse biasing raises the threshold voltages and thus reduce the subthreshold currents and saves power in standby mode.

4 973 Fig8, a) General b) Swapped c) Tunable d) DTMOS Configuration body biasing body biasing Above figure shows various body biasing techniques applied to a inverter. In swapped body biasing (SBB), the devices do not effectively turn OFF and would thus dissipate power even when there is no useful work being performed. So we can go for DTMOS configuration, where the bulk of each transistor is tied to its gate. So the subthreshold current increases when the devices are turned ON and reduces these currents when the devices are in their OFF state. Sometime we need to perform our operation in both subthreshold and above threshold configuration. In that case we go for tunable body biasing. Here the controlling signals are generated through a multiplexer. SBB and DTMOS techniques are applicable only in subthreshold region of operation [7]. 4. PERFORMANCE ANALYSIS OF 9 STAGE RING OSCILLATOR USING PARALLEL STACKING (PS) AND BODY BIASING (BB) TECHNIQUE Oscillators are used for synchronizing computation in a digital system, timing the sampling in a data converter, carrier synthesis and LO in RF systems, etc... Fig9. Ring Oscillator Fig10. PN-PTS CMOS inverter So improving the performance of these oscillators at subthreshold operation is of prime importance. In our analysis we will be using a inverter consisting of large transistors with widths of 0.96 and 0.48µm for PMOS and NMOS transistors, respectively. A ring oscillator can be designed by connecting odd no of inverters as shown above. Since we are dealing with 45nm technology the optimum width of both NMOS and PMOS are found to be 120nm. So if we apply parallel stacking technique there will be 8 parallel stacks of PMOS transistor and 4 parallel stacks of NMOS transistor. In body biasing techniques SBB and DTMOS configurations are chosen. TABLE1: Ring oscillator frequency variation using parallel stacking Configuration/Voltage(V) STANDARD P-PTS N-PTS PN-PTS KHz 2110 KHz 1750 KHz 2900 KHz TABLE2: Ring oscillator frequency variation using body biasing Configuration/Voltage(V) DYNAMIC BODY BIASING SWAPPED BODY BIASING KHz 3164 KHz In N-PTS and P-PTS only NMOS and PMOS transistors are parallel stacked respectively. From the above table we can conclude that in Parallel configuration (i.e., PN-PTS) inverter is faster than the other configurations. In body biasing techniques swapped body biasing is faster than all. But when both of them are compared swapped body biasing is more efficient. Each of these techniques has their own limitations. For example using parallel stacking area overhead increases and by using swapped body biasing technique average power increases. So depending on our requirements we can use either of the techniques. 5. DESIGN OF64-BIT STREAM CIPHER USING PROPOSED TECHNIQUE Earlier we have seen that how current in the circuits can be increased by parallel stacking and body biasing technique. So now we can combine these two techniques in order to improve the speed of the circuits. Analysis of

5 bit stream cipher using standard, body biasing, parallel stacking and combination of these two techniques is shown below Fig11. Practical Stream Cipher Fig bit LFSR Symmetric cryptography is split into block ciphers and stream ciphers. Stream ciphers encrypt bits individually. This is achieved by adding a bit from a key stream to a plaintext bit. There are synchronous stream ciphers where the key stream depends only on the key and asynchronous ones where the key stream also depends on the cipher text. Most practical stream ciphers are synchronous ones. In general we use LFSR (Linear feedback shift registers) for generation of this key stream. So we will be applying the various design techniques discussed so far and will compare the delay and average power dissipation in each case. We have chosen a 64 bit lfsr as our design example. In order to get maximum test patterns generated the tap positions are chosen at 64,63,61,60 respectively. In the above fiqure12 each rectangle box is master slave flipflop with an initialization circuit. For sake of simplicity each circuit is initialized to be 1. Depending on this initialization circuit and the tap positions (initial state of the flipflops) test patterns are generated. Following circuitry is used for designing of each flipflop. While analyzing different techniques all the basic gates are designed using respective technique. For example when we are designing stream cipher using parallel stacking technique, then all the nand, inverter, or, xor gates are designed using parallel stacking technique. Similar is the case with body biasing. By using parallel stacking technique area Fig13. Master slave flipflop with initialization circuit Fig14. Waveform of 64 bit stream cipher Fig15. Layout of 64 bit stream cipher

6 975 In table 3 delay is calculated by taking difference between time at which output signal (rising/falling edge) is changing with respect to the corresponding change in input signal. Ideally we want the delay to be zero i.e. output signal should change immediately according to the change in input signal. But practically it doesn t happen and delay will be there. TABLE3: Delay and power analysis of stream cipher and other basic gates using various design techniques CIRCUIT (VDD=0.3) DESIGN TECHNIQUE DELAY AVERAGE POWER STATIC POWER IMPROVEMT IN DELAY Normal 9.99n 5.74p 0.71p INVERTER Body biasing(bb) 3.2n 8.4p 3.92p Parallel stacking(ps) 8.47n 12.34p 0.98p Combination of BB and PS 3.02n 25.66p 4.81p 70% Normal 47.31n 6.24p 0.26p NAND (2input) Body biasing(bb) 14.99n 8.75p 1.44p Parallel stacking(ps) 39.87n 17.15p 0.37p Combination of BB and PS 14.44n 21.06p 1.67p 70% Normal 166n 21.72p 2.8p XOR(2input) NOR (2input) STREAM CIPHER Body biasing(bb) 46.2n 38.27p 15p Parallel stacking(ps) 102.3n 60.03p 5.34p Combination of BB and PS 35.69n 83.45p 25p 79% Normal 6.28n 6.73p 1.4p Body biasing(bb) 2.04n 8.34p 7.84p Parallel stacking(ps) 5.59n 16.26p 1.97p Combination of BB and PS 1.92n 21.69p 9.62p 69% Normal 500n 5.84n 1.61n Body biasing(bb) 129.5n 14.9n 8.8n Parallel stacking(ps) 310.8n 18.2n 3.01n Combination of BB and PS 108.5n 25.3n 13.9n 78% 6. CONCLUSION Parallel stacking technique is one of the methods to improve the performance of the system in subthreshold operated circuits where the energy consumption should be minimum. Limitation of this technique is if the size of NMOS/PMOS transistors is more then there will be more number of parallel transistors so the area overhead will increase. Similarly body biasing technique can be used where there is no concern about power dissipation. A new technique has been proposed where speed of the circuits can be improved upto 70%. If area and power dissipation are not considered then this is one of the efficient techniques to increase speed of the circuits in subthreshold region. Any digital circuit can be designed using the Universal gates like NAND, NOR. By increasing the efficiency of these gates the overall performance of any circuit can be improved. By the proposed technique delay of the basic gates and stream cipher (designed by using these basic gates) has been improved by 70%. So depending on our requirement we can use any one of the above techniques. Using latest technology and newer design techniques further modification can be implemented. REFERENCES [1] Wang, A., Calhoun, B.H., and Chandrakasan, A.P.: Sub-threshold design for ultra low Power systems'(springer, 2006). [2] M. Muker and M. Shans, Designing digital subthreshold CMOS circuits using parallel transistor stacks, IET Electronics Letter, vol. 47,no.6, pp , March [3] Akers, L.A.: The inverse-narrow-width effect, IEEE Electron Device Lett., 1986, 7, (7), pp [4] Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand Leakage current mechanisms and leakage reduction techniques in deep Sub micrometer cmos circuits Proceedings of the IEEE, vol. 91, no. 2, February [5] Xinfu, L., Kheeyong, L., Zhihua, W., Zhibin, X., Yongping, D., Hao, N., Yanping, W., Yanping, S., Bin, T., Louis, L., Sally, C., Xing, Y., Feng, H., and Yang, S.: A study of inverse narrow width effect of 65nm low power CMOS technology. 9th Int. Conf. on Solid-State and Integrated-Circuit Technology, (ICSICT), Beijing, China, October 2008, pp [6] S. Chung and C.-T Li, An analytical threshold-voltage model of trench-isolated MOS devices with non uniformly doped substrates, IEEE Trans. Electron Devices, vol. 39, pp , Mar [7] Jabulani Nyathi; Sch. of EECS, Washington State Univ., Pullman, WA; Bero.B LOGIC CIRCUITS OPERATING IN SUBTHRESHOLD VOLTAGES Low Power Electronics and Design, ISLPED 06. Proceedings of the 200 International Symposiums.