Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology

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1 Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology Shyam Sundar Sharma 1, Ravi Shrivastava 2, Nikhil Saxenna 3 1Research Scholar Dept. of ECE, ITM, Gwalior, India 2Assistant Professor, Dept. of ECE, ITM, Gwalior, India 3Assistant Professor, Dept. of ECE, ITM, Gwalior, India ABSTRACT In the present day scenario, it has become a challenge to reduce static power dissipation as we are progressing towards the nano - scale domain. Inter-die and intra-die variations and varied short channel effects also come into existence. Innovative and holistic circuit level methodology is required to trade between area, power, frequency, robustness and quality while maintaining an ample manufacturing yield. An alternative solution to the bulky devices is the proposed FinFET device. Many approaches have been earlier to minimize the static power dissipation, but they were only able to minimize a fraction of leakage current. In this paper, we have proposed a MTCMOS technique and implemented it on FinFET based 6T SRAM cell. The proposed technique reduces the power dissipation significantly in stand-by mode. The simulation to observe variations in leakage current and leakage power was carried out in Cadence Virtuoso Tool at 45 nm technology. KEYWORDS SRAM, FinFET, MTCMOS, Leakage current, Leakage power. I. INTRODUCTION In modern nano-scale CMOS integrated circuits, leakage currents are important sources of power consumption. Continuous lowering of scaling technology day by day, results in shrinking of the feature sizes and miniaturization at chip level has occurred [1]. To store a large amount of digital information semiconductor memory arrays is required. The amount of memory is always depends on the application for which it is used. The need of Static Random Access Memories (SRAMs) is increasing day by day with huge use of SRAM in SoC and high performing VLSI circuits. CMOS circuits are scaled down continuously due to need of battery operated devices. These days Nano-scale CMOS based memory design are facing acute challenges like reduction in noise margin and rising variability. SRAMs are volatile in nature. By the use of CMOS technology designers have made several architectural level designs of chips for higher integration and faster operation. Low power operations have become an important feature for today s microprocessors. The most significant ways to meet these objectives are to design ultra-low power SRAM cells [2]. In standby mode the leakage current of the memory will get increased due to increase in the capacity due to which more power will be consumed. For high performance, these onchip memory cells are usually embedded with an array of highly dense packed SRAM cells. Static power dissipation caused due to standby leakage currents, is an important component of total power dissipation. Many electronics devices contain different types of component out of which many remain idle during a particular operation. Static power dissipation occurring in these idle components resembles a huge percentage of total power dissipation in the system. Therefore, minimization of this leakage component becomes essential for effective power management. II. FinFET In recent years FinFET technology redefined the entire chipset industry with newly implemented 3D transistors. FinFET, which is also known as Fin Field Effect Transistor, is a type of non-planar or 3D transistor used in the design of modern processors. The Berkeley researchers (Profs. Chenming Hu, Tsu- Jae King-Liu and Jeffrey Bokor) of California University invented the term FinFET, to define a non-planar, double-gate transistor built on ISSN: Page 303

2 an SOI substrate. In FinFET the conducting channel is encased by a thin silicon "fin", which forms the body of the device. The effective channel length of the device determined by the thickness of the fin which is valuated in the direction from source to drain. The most important property of the FinFET is as follows first the conducting channel is covered by thin silicon fin that forms the upper part of the device. The main channel length of the device is triggered by the width of the fin. FinFET has good control over the current because of multiple gates, which is use full in reducing the short channel effects and it reduces the Leakage Current which is present in Sub Threshold region of MOSFET devices [3]. FinFET has good cut-off characteristics and greater scalability [4]. III. CONVENTIONAL 6T FINFET SRAM CELL The structure of the conventional 6T SRAM Cell made of FinFETs is shown in Fig.1 The 6T SRAM cell is made by using six transistors (two PMOS and two NMOS), in which four transistors (two PMOS and two NMOS) form a latch and two NMOS are the pass transistors. The two PMOS (P1 and P2) and two NMOS (N1 and N2) form two inverters which are connected back to back. The other two NMOS transistors (N3 and N4) are the access transistors which are enabled through word line (WL). The two bit lines (BL and BLB) and word line (WL) are used for performing read and write operations [5]. The source terminals of access transistors are attached to bit lines (BL and BLB), and drain terminals are connected to latch inputs. Word line (WL) is connected to the gate terminal of access transistors N3 and N4 [6]. Access transistors are disabled, when the word line is low, and read or write operations cannot be performed at this time, and hold state is acquired. Access transistors are enabled when the word line becomes high, and read and write operations can be performed at this stage [7] ISSN: Page 304

3 WL Vdd P1 P2 N3 N4 N1 N2 BL GND BLB Fig 1: FinFET based 6T SRAM Cell IV. MTCMOS TECHNIQUE EMPLOYED 6T FINFET SRAM CELL MTCMOS is a multi-threshold CMOS technique. It is a technique where a high V t (threshold voltage) transistors are inserted between the power supply and logic circuit or between logic circuit and ground or both. This results in the creation of virtual supply or virtual ground respectively [8]. The logic circuit blocks consist of low V t transistors. The reason for imposing low V t components in logic blocks is fast switching speed and high V t header and footer to minimize the leakage. This technique is most effective in reducing standby leakage [9]. The structure of the MTCMOS technique employed 6T SRAM Cell made of FinFETs is shown in Fig.2. ISSN: Page 305

4 Vdd SLEEP WL P1 P2 N3 N4 N1 N2 BL BLB SLEEP Fig 2: MTCMOS Technique employed FinFET based 6T SRAM Cell V. RESULTS The simulation of of circuits having MTCMOS technique employed FinFET based 6T SRAM cell as its basic unit cell has been done in cadence virtuoso tool at 45 nm technology. The leakage parameter of MTCMOS technique employed FinFET based 6T SRAM cell has been calculated at different supply voltages of 0.6V, 0.7V, 0.8V and 0.9V. In figures the simulated Leakage Current and Leakage Power waveform of FinFET based 6T SRAM and simulation for reduced Leakage Current and Leakage Power waveform through MTCMOS technique are shown. ISSN: Page 306

5 Fig 3: Leakage Current of FinFET based 6T SRAM cell Fig 5: Leakage Current of FinFET based 6T MTCMOS SRAM cell Fig 4: Leakage Power of FinFET based 6T SRAM cell Fig 6: Leakage Power of FinFET based 6T MTCMOS SRAM cell ISSN: Page 307

6 Leakage Power Leakage Current International Journal of Engineering Trends and Technology (IJETT) Volume-42 Number-6 - December 2016 Table 1 COMPARISON of LEAKAGE CURRENT PARAMETER Voltage (V) 6T SRAM (fa) 6T MTCMOS SRAM (fa) T SRAM Voltage (Volts) Shows Table 1 in this table representing parameters of Conventional 6T FinFET SRAM, and MTCMOS based 6T FinFET SRAM and find that MTCMOS based 6T FinFET SRAM has reduced the value of Leakage Current. Table 2 COMPARISON of LEAKAGE POWER PARAMETER Fig 7: Graphical representation of Table 1. Shows Fig. 7 it represents a graph of Conventional 6T FinFET SRAM and MTCMOS based 6T SRAM technique at different supply voltages (0.6V, 0.7V,0.8 and 0.9V) and find that MTCMOS based 6T SRAM has a reduced graph of Leakage Current. 35 Voltage (V) 6T SRAM (nw) 6T MTCMOS SRAM (nw) T SRAM Voltage (Volts) Fig 8: Graphical representation of Table 2. Shows Table 2 in this table representing parameters of Conventional 6T FinFET SRAM and MTCMOS based 6T FinFET SRAM and find that MTCMOS based 6T FinFET SRAM has reduced the value of Leakage Power. Shows Fig. 8 it represents a graph of Conventional 6T FinFET SRAM and MTCMOS based 6T SRAM technique at different supply voltages (0.6V, 0.7V,0.8 and 0.9V) and find that MTCMOS based 6T SRAM has a reduced graph of Leakage Power. ISSN: Page 308

7 CONCLUSION In this paper we have designed simple 6T FinFET SRAM cell and MTCMOS technique employed 6T FinFET SRAM cell at 45 nm technology with the help of cadence virtuoso tool. It is observed that in MTCMOS technique employed 6T FinFET SRAM cell leakage current reduces to fa from fa, and leakage power reduces to nw from nw at 0.7V that shows in our proposed technique we get % less leakage current and % less leakage power.according to the these parameters and observing the above tables and graphs it is concluded that MTCMOS technique based 6T FinFET SRAM is better than the simple 6T FinFET SRAM because leakage current and leakage power reduction is better in MTCMOS based 6T FinFET SRAM. Journal of Computer Science and Information Technologies (IJCSIT), Vol. 3(3), 2012, [9] Dong Whee Kim, Jeong Beom Kee, LowPower Carry Look- Ahead Adder With MultiThreshold Voltage CMOS Technology, in Proceeding of ICSICT International Conference on Solid-State and Integrated Circuit Technology, pp , 2008 ACKNOWLEDGEMENT This work has been supported by ITM University, Gwalior in collaboration with Cadence virtuoso Design System, Bangalore India. REFERENCES [1] Azizi,N., NajmF.N and Moshovos A, "Low-leakage asymmetric-cell SRAM,", IEEE Transactions on Very Large Scale Integration (VLSI) System, vol. 11, no. 4, pp , [2] M. Alioto, Ultra low power VLSI circuits design demystified and explained: A tutorial, IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 59, no.1, pp. 3-29, [3] Viadyanathan Subramanian, Multiple Gate Field-Effect Transistors for Future CMOS Technologies, IETE Technical review, vol. 27, issue. 6, pp , [4] K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano, T. Ono, K. Yahashi, K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba, K. Ishimaru, K. Suguro, K. Eguchi, Y. Tsunashima and H. Ishiu, Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length, IEEE international conference on IEDM technical digest, pp , [5] Gupta And M. Anis, Statistical Design Of The 6T SRAM Bit Cell, IEEE Trans. Circuits Syst.- I, Vol. 57, No. 1, Pp , Mar [6] Pankaj Agarwa, Nikhil Saxena, Nikhita Tripathi, Low Power Design and Simulation of 7T SRAM Cell using various Circuit Techniques, International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue5- May [7] PN Vamsi Kiran, Nikhil Saxena, Design and analysis of different types SRAM cell topologies, Electronics and Communication Systems (ICECS), nd International Conference on, pp , [8] Phanikumar M and N. Shanmukha Rao, A Low Power and High Speed Design for VLSI Logic Circuits Using Multi- Threshold Voltage CMOS Technology, International ISSN: Page 309