Low Power Design Part I Introduction and VHDL design. Ricardo Santos LSCAD/FACOM/UFMS

Transcription

1 Low Power Design Part I Introduction and VHDL design Ricardo Santos ricardo@facom.ufms.br LSCAD/FACOM/UFMS

2 Motivation for Low Power Design Low power design is important from three different reasons Device temperature Failure rate, Cooling and packaging costs Life of the battery Meantime between charging, System cost Environment Overall energy consumption

3 ISSCC, Feb. 2001, Keynote Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP. Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second about the same number of calculations that the world's fastest supercomputer can perform now. Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....

4 Distribution of energy dissipation across pipeline stages In order processor: Fetch: 37% Decode: 18% Issue: 14% Execute: 9% Memory: 15% Writeback: 7%

5 Low-Power Design Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: Algorithms and architectures High-level and software techniques Gate and circuit-level methods Test power

6 Power Projections Sun s Surface Power Density (W/cm2) 1000 Rocket Nuclear Nozzle 100 Reactor 8086 Hot Plate P Pentium

7 Basics Power Direct impact on instantaneous energy consumption and temperature Energy Power integrated over time is energy and impact on battery shelf life and environment T E(T) = P(t) dt 0

8 Basics Dynamic Transition Short circuit Leakage Sub-threshold leakage Diode/Drain leakage Gate leakage At 250nm leakage power was only 5% but it is increasing rapidly as geometries decrease

9 Dynamic Energy Consumption Transition Power Vdd Vin Vout C L Energy/transition = C L * V DD 2 * P 0 1 Power Switching = α * C L * V DD 2 * f Power Switching is called Dynamic Power.

10 Low Power Design Approaches System design: Top down Effective low power transformations in synthesis Fast estimation techniques for an effective exploration of a large design space Cell library design: Bottom up Low power circuit design techniques Accurate estimation Effective models for synthesis tools

11 Design Levels System Algorithmic/Module RTL Gate Circuit Device technology

12 System Level Design Same embedded application running on different systems consume significantly different amounts of power System partitioning Buses/Memory/IO devices /interfaces Choice of components Coding System states (sleep/snooze etc) DVS/DFS/..

13 Algorithmic/sub-system Level Choice of algorithm (operation count etc.) Word length choices Module interfaces Implementation technology SW: Processor selection HW: ASIC/FPGA/.. Behavioral synthesis constraints and trade-off

14 RTL Pipelining/retiming Module selection Multiple frequency and voltage islands Reduction in switching activity through transformations

15 Gate Level Clock gating Power gating Clock tree optimization Logic level transformations to reduce switching activity

16 Circuit Level Transistor sizing Power efficient circuits Cell design Multi-threshold circuits

17 Device Technology Multi-oxide devices Multiple cell types on a single substrate Logic, SRAM, Flash etc. Support for many other low power design techniques (multiple thresholds, multiple voltages, multiple frequencies etc.)

18 VHDL for Low Power Guidelines and good practices for writing efficient RTL code from a low-power standpoint Techniques: Glitch Reduction Clock gating LP for FSMs LP for Datapaths Precomputation Guarded Evaluation

19 VHDL for Low Power Glitch Reduction Due to converging combinatorial paths with different propagation delays Glitches are not an issue for power consumption only Also affect the signal integrity and the timing closure with effects like dynamic cross talk Example: multiplexers for a full-adder

20 VHDL for Low Power Clock Gating Disable or suppress transitions from propagating to parts of the clock path under a certain condition computed by clock gating circuits Example: Clock gating register file

21 VHDL for Low Power Low Power for FSMs circuits Gate-clock FSM for freezing the clock and the input signals when staying at the same state State encoding based on gray code for minimizing the hamming distance on the transitions from one state to another Same challengers of branch prediction techniques!

22 VHDL for Low Power Low Power for Datapaths Precomputation design techniques identifying a logic condition on some inputs of a combinational circuit for which the output does not vary Guarded evaluation is applicable to embedded combinational blocks from which outputs are in idle condition Insertion of transparent latches

23 Conclusions Low power is one of the most important issues for processor designers Conflicting goals sometimes There are previous research considering low power on instruction encoding Curiously, current research is focusing on accelerators along with the datapath to power reduction