Interconnect/Via CONCORDIA VLSI DESIGN LAB
|
|
- Madeline Lewis
- 5 years ago
- Views:
Transcription
1 Interconnect/Via 1
2 Delay of Devices and Interconnect 2
3 Reduction of the feature size Increase in the influence of the interconnect delay on system performance Skew The difference in the arrival times of the clock signal to all registers in a synchronous digital system 3
4 An Example, The Clock Distribution Network (CDN) A set of interconnections that delivers reliably a time reference, clock signal, to every register element in a synchronous digital system. PowerPC microprocessor 32,000 master/slave latch 4
5 Power Consumption &Routing and system complexity P= CV 2 f Short-Circuit Leakage 6% 6% Global Interconnect 8% 11% I/O 12% 3% Clock Memory 54% Logic and Local Routing 5
6 Delay model of the CDN, Elmore Delay model er 0 It takes into account the interconnect resistance and capacitance and the capacitance of the registers ec 0/ /2 ec 0/ /2 s 0 r 1 s 1 r 2 s 1 s 2 s 0 s 2 r 3 r 1 r 2 r 3 r 4 r 4 6
7 Example: Routing delay problems The Clock Skew The difference between time arrivals of the clock signal to all the registers in a synchronous digital system In R i T i T PD(min) /T PD(max) R j T j Out S(ij) = T i - T j Two conditions: S(ij) T HOLDj - T PD(min) Race Conditions Permissible range Clock Period Limitations S(ij) T clk - T PD(max) S(ij) min S(ij) max 7
8 Minimizing the effects of delay, The H_Tree If it is possible to divide the set of registers R into two symmetric sets recursively and alternatively by vertical and horizontal lines, then the set R can be connected by an H-tree 8
9 Interconnect Length 9
10 Interconnect/Via 10
11 Cross Section View of Capacitances in interconnect Units are in Angstrom, 1A=0.1nm 11
12 Interconnect Interconnects in chips are routed in several layers horizontally and vertically and used according to their application 12
13 Small line length: transistor speed governs the circuit speed. Medium line length Transistor output resistance and line capacitance govern the circuit speed. Long line length, line resistance and line capacitance govern the circuit speed. Cooling the room temperature to 77K reduces the resistivity by an order of magnitude. At higher frequencies, Ghz and above the skin effect has to be taken into account.
14 Interconnect usage Local interconnect are used for short distances on the chip. Mainly to connect the device Drain, source, gates or immediate devices. Semi_global interconnect is used to connect gates FFs other small devices within a block of the hierarchy. Global wiring is used for long interconnect such as Clock signal or other control signals. Separating the interconnect wires and the devices from each other are the dielectric material. The dielectric material gets thicker as move higher in the hierarchy of the wire placement
15 Parallel and fringing Capacitance 15
16 Fringing Capacitance ance.html
17 Fringing Capacitance T is the thickness of wire H is the distance of wire to substrate. C F r * 2H T ln(1 (1 1 )) T H T 4H 17
18 Cross Talk 18
19 Cross talk Is a disturbance caused by the electric or magnetic fields of one telecommunication signal affecting a signal in an adjacent circuit. Two effects: increased capacitance on the driver. Introduction of unwanted signal or noise from one line to the other. Design tips: Methods to reduce cross talk, Increase inter_wire spacing. Place Vdd or ground wires between signal lines.
20 Fringing/ Parallel Plate Capacitance of Interconnect 20
21 Modeling Interconnect LUMPED MODEL T-MODEL -MODEL 2T-MODEL 2π -MODEL 21
22 Modeling of Interconnect 22
23 Delay of Interconnect delay rcl 2 2 delay rc N( N 1) 2 Capacitance = C/unit area * L (length) * W (width) = C Resistance = R/ * number of squares = R 23
24 Delay comparison Voltage Range Lumped RC Distributed RC 0 50% 0.69RC 0.38RC 0 63% RC 0.5RC 10 90% 2.2RC 0.9RC 24
25 RC delay with distributed parameters: More accurate than lumped RC model More difficult to solve for large N Need full-scale SPICE simulation
26 Example A signal is propagated on a 6mm length metal 1 (M1) interconnect of CMOSIS5 Process, using minimum wire width. Calculate the delay and comment on methods for reducing this delay. 6mm Now the resistance and capacitance of CMOSIS5 are given as (from the manual): r = 0.07 W / c = 46 af/µm 2, c = 46*1 exp -18, (a = 1 exp -18), 26
27 Rent s rule, relates number of i/o pins T, to the number of gates N in a random logic network: T T=kN**p Where: k = average I/O per gate P= Rent s exponent. It reflects wiring complexity, p=1 is the highest.
28 What is the maximum size of silicon chip? Power dissipation Packaging Number of pins Technology The interconnect used A chip 0.16 R R C o int C o int C ln( INT Area 2 C packaging o C l ) 28
29 Thank you! 29
30 Inductances For die wires L 4h ln( ) 2 d h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material 30
31 Inductance For on-chip, L 8h w ln( ) 2 w 4h h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material 31
32 Ground Bounce and Vdd Sag examples from Alterahttp:// 32
33 Example on V DD Bounce Determine the values of due to inductive and resistive losses x, y when the output driver sources 10mA in 1.5ns in the following circuit. Assume inductance of 13.9nH/mm. 33
34 Board Vdd Circuit Vdd Board Gnd Circuit Gnd 34
35 Example on Power lines What will be the power line width if you drive a 10pF load at 1GHz Assume Vdd=3.5V. 35
36 Example on Charge Sharing Calculate the drop in voltage for 64 read lines each consisting of 0.1pF capacitances. Assume bus capacitance to be 10pF. 36
37 Thank you! 37
Chapter 4. Problems. 1 Chapter 4 Problem Set
1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock network (between the nodes) is 5 mm long, 3 µm wide, and is implemented
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 11: Wires, Elmore Delay
EE115C Winter 2017 Digital Electronic Circuits Lecture 11: Wires, Elmore Delay The Wire transmitters receivers schematics physical EE115C Winter 2017 2 Interconnect Impact on Chip EE115C Winter 2017 3
More informationLecture 13: Interconnects in CMOS Technology
Lecture 13: Interconnects in CMOS Technology Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/18/18 VLSI-1 Class Notes Introduction Chips are mostly made of wires
More informationLecture #2 Solving the Interconnect Problems in VLSI
Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology
More informationEE434 ASIC & Digital Systems. Partha Pande School of EECS Washington State University
EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 11 Physical Design Issues Interconnect Scaling Effects Dense multilayer metal increases coupling
More informationEE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.
EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL
More informationPower and Energy. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
Power and Energy Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu The Chip is HOT Power consumption increases
More informationELEC Digital Logic Circuits Fall 2015 Delay and Power
ELEC - Digital Logic Circuits Fall 5 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal
More informationInterconnect-Power Dissipation in a Microprocessor
4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition
More informationSignal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
More informationInterconnect. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
Interconnect Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Introduction Chips are mostly made of wires called
More informationPROGRAMMABLE ASIC INTERCONNECT
PROGRAMMABLE ASIC INTERCONNECT The structure and complexity of the interconnect is largely determined by the programming technology and the architecture of the basic logic cell The first programmable ASICs
More informationDesign Challenges in Multi-GHz Microprocessors
Design Challenges in Multi-GHz Microprocessors Bill Herrick Director, Alpha Microprocessor Development www.compaq.com Introduction Moore s Law ( Law (the trend that the demand for IC functions and the
More informationTiming analysis can be done right after synthesis. But it can only be accurately done when layout is available
Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate
More informationECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics
ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.
More informationEE141-Spring 2007 Digital Integrated Circuits
EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon
More informationEffect of Aging on Power Integrity of Digital Integrated Circuits
Effect of Aging on Power Integrity of Digital Integrated Circuits A. Boyer, S. Ben Dhia Alexandre.boyer@laas.fr Sonia.bendhia@laas.fr 1 May 14 th, 2013 Introduction and context Long time operation Harsh
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationLecture 13 CMOS Power Dissipation
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 13 CMOS Power Dissipation Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken,
More informationReference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering
FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 CPLD / FPGA CPLD Interconnection of several PLD blocks with Programmable interconnect on a single chip Logic blocks executes
More informationDeep Submicron Interconnect. 0.18um vs. 013um Interconnect
Deep Submicron Interconnect R. Dept. of ECE University of British Columbia res@ece.ubc.ca 0.18um vs. 013um Interconnect 0.18µm 5-layer Al Metal Process 0.13µm 8-layer Cu Metal Process 1 Interconnect Scaling
More informationif the conductance is set to zero, the equation can be written as following t 2 (4)
1 ECEN 720 High-Speed Links: Circuits and Systems Lab1 - Transmission Lines Objective To learn about transmission lines and time-domain reflectometer (TDR). Introduction Wires are used to transmit clocks
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More informationLecture 9: Cell Design Issues
Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the
More informationLow Power Design in VLSI
Low Power Design in VLSI Evolution in Power Dissipation: Why worry about power? Heat Dissipation source : arpa-esto microprocessor power dissipation DEC 21164 Computers Defined by Watts not MIPS: µwatt
More informationECE 497 JS Lecture - 22 Timing & Signaling
ECE 497 JS Lecture - 22 Timing & Signaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements - Signaling Techniques (4/27) - Signaling
More informationUNISONIC TECHNOLOGIES CO., LTD L16B06 Preliminary CMOS IC
UNISONIC TECHNOLOGIES CO., LTD L16B06 Preliminary CMOS IC 16-BIT CONSTANT CURRENT LED DRIVER DESCRIPTION The L16B06 is a constant-current sink driver specifically designed for LED display applications.
More informationPROGRAMMABLE ASIC INTERCONNECT
ASICs...THE COURSE (1 WEEK) PROGRAMMABLE ASIC INTERCONNECT 7 Key concepts: programmable interconnect raw materials: aluminum-based metallization and a line capacitance of 0.2pFcm 1 7.1 Actel ACT Actel
More informationLow Power VLSI CMOS Design. An Image Processing Chip for RGB to HSI Conversion
REPRINT FROM: PROC. OF IRISCH SIGNAL AND SYSTEM CONFERENCE, DERRY, NORTHERN IRELAND, PP.165-172. Low Power VLSI CMOS Design An Image Processing Chip for RGB to HSI Conversion A.Th. Schwarzbacher and J.B.
More informationECE 546 Lecture 20 Power Distribution Networks
ECE 546 Lecture 20 Power Distribution Networks Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 IC on Package ECE 546
More informationLow-Power Digital CMOS Design: A Survey
Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with
More informationProgrammable Interconnect. CPE/EE 428, CPE 528: Session #13. Actel Programmable Interconnect. Actel Programmable Interconnect
Programmable Interconnect CPE/EE 428, CPE 528: Session #13 Department of Electrical and Computer Engineering University of Alabama in Huntsville In addition to programmable cells, programmable ASICs must
More informationIntroduction to CMOS VLSI Design (E158) Lecture 9: Cell Design
Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture
More information2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
More informationSignal Integrity for Gigascale SOC Design. Professor Lei He ECE Department University of Wisconsin, Madison
Signal Integrity for Gigascale SOC Design Professor Lei He ECE Department University of Wisconsin, Madison he@ece.wisc.edu http://eda.ece.wisc.edu Outline Capacitive noise Technology trends Capacitance
More informationEE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits
EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R R 6 W 1 C C 3 D R t 1 R R t 2 R R t
More informationECE 301 Digital Electronics
ECE 301 Digital Electronics Constraints in Logic Circuit Design (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and
More information16-bit Constant Current LED Driver with Error Detection
: _ENG_V11 Version Issue Date : 2008/05/08 File Name : _ENGpdf Total Pages : 20 16-bit Constant Current LED Driver with Error Detection 16-bit Constant Current LED Driver with Error Detection General Description
More informationMicrocontroller Systems. ELET 3232 Topic 13: Load Analysis
Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission
More informationTiming Issues in FPGA Synchronous Circuit Design
ECE 428 Programmable ASIC Design Timing Issues in FPGA Synchronous Circuit Design Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 1-1 FPGA Design Flow Schematic capture HDL
More informationECE380 Digital Logic
ECE380 Digital Logic Implementation Technology: Standard Chips and Programmable Logic Devices Dr. D. J. Jackson Lecture 10-1 Standard chips A number of chips, each with a few logic gates, are commonly
More informationEE141- Spring 2004 Digital Integrated Circuits
EE141- Spring 2004 Digital Integrated Circuits Lecture 27 Power distribution Resistive interconnect 1 Administrative Stuff Make-up lecture on Monday 4-5:30pm Special office hours of Prof. Rabaey today
More informationFigure 1. Inductance
Tools for On-Chip Interconnect Inductance Extraction Jerry Tallinger OEA International Inc. 155 East Main Ave., Ste. 110 Morgan Hill, CA 95037 jerry@oea.com Haris Basit OEA International Inc. 155 East
More informationVLSI Design I; A. Milenkovic 1
CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f
More informationLecture 4&5 CMOS Circuits
Lecture 4&5 CMOS Circuits Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese566/ Worst-Case V OL 2 3 Outline Combinational Logic (Delay Analysis) Sequential Circuits
More informationMicrocircuit Electrical Issues
Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the
More informationVLSI is scaling faster than number of interface pins
High Speed Digital Signals Why Study High Speed Digital Signals Speeds of processors and signaling Doubled with last few years Already at 1-3 GHz microprocessors Early stages of terahertz Higher speeds
More informationDigital Integrated Circuits Lecture 20: Package, Power, Clock, and I/O
Digital Integrated Circuits Lecture 20: Package, Power, Clock, and I/O Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec20 cwliu@twins.ee.nctu.edu.tw
More informationINF8574 GENERAL DESCRIPTION
GENERAL DESCRIPTION The INF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I 2 C). The device consists
More informationPI6C49X0204A. Low Skew 1 TO 4 Clock Buffer. Features. Description. Block Diagram. Pin Assignment
Features ÎÎLow skew outputs (250 ps) ÎÎPackaged in 8-pin SOIC ÎÎLow power CMOS technology ÎÎOperating Voltages of 1.5 V to 3.3 V ÎÎOutput Enable pin tri-states outputs ÎÎ3.6 V tolerant input clock ÎÎIndustrial
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationHMC677G32 INTERFACE - SMT. 6-Bit SERIAL/PARALLEL SWITCH DRIVER/CONTROLLER. Typical Applications. Features. Functional Diagram. General Description
Typical Applications The is ideal for: Microwave and Millimeterwave Control Circuits Test and Measurement Equipment Complex Multi-Function Assemblies Military and Space Subsystems Transmit/Receive Module
More informationPropagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationPropagation Delay, Circuit Timing & Adder Design
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationEE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector
EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1 Table
More informationChapter 2 Combinational Circuits
Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits
More information1 Gb DRAM. 32 Mb Module. Plane 1. Plane 2
Design Space Exploration for Robust Power Delivery in TSV Based 3-D Systems-on-Chip Suhas M. Satheesh High-Speed Fabrics Team NVIDIA Santa Clara, California 955 ssatheesh@nvidia.com Emre Salman Department
More informationOptimization of Power Dissipation and Skew Sensitivity in Clock Buffer Synthesis
Optimization of Power Dissipation and Skew Sensitivity in Clock Buffer Synthesis Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, and Ting-Ting Lin Department of Computer Science and Engineering Mail Code 0114
More informationLow Power Design Part I Introduction and VHDL design. Ricardo Santos LSCAD/FACOM/UFMS
Low Power Design Part I Introduction and VHDL design Ricardo Santos ricardo@facom.ufms.br LSCAD/FACOM/UFMS Motivation for Low Power Design Low power design is important from three different reasons Device
More informationLecture 10. Circuit Pitfalls
Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski
More information1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)
CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,
More informationLow current consumption : 0.4 ma typ. Driver output current : 70 ma max. 5 MHz (cascade connection) Selectable H/L for latch and driver enable
The is a CMOS thermal print head driver containing a 64-bit shift register and a latch. It can be used for general purpose because H or L can be selected for the latch and the driver enable. It is ideal
More informationPower Spring /7/05 L11 Power 1
Power 6.884 Spring 2005 3/7/05 L11 Power 1 Lab 2 Results Pareto-Optimal Points 6.884 Spring 2005 3/7/05 L11 Power 2 Standard Projects Two basic design projects Processor variants (based on lab1&2 testrigs)
More informationSignal integrity means clean
CHIPS & CIRCUITS As you move into the deep sub-micron realm, you need new tools and techniques that will detect and remedy signal interference. Dr. Lynne Green, HyperLynx Division, Pads Software Inc The
More information2.5D & 3D Package Signal Integrity A Paradigm Shift
2.5D & 3D Package Signal Integrity A Paradigm Shift Nozad Karim Technology & Platform Development November, 2011 Enabling a Microelectronic World Content Traditional package signal integrity vs. 2.5D/3D
More informationDigital Design and System Implementation. Overview of Physical Implementations
Digital Design and System Implementation Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops
More informationPhil Lehwalder ECE526 Summer 2011 Dr. Chiang
Phil Lehwalder ECE526 Summer 2011 Dr. Chiang PLL (Phase Lock Loop) Dynamic system that produces a clock in response to the frequency and phase of an input clock by varying frequency of an internal oscillator.
More informationMeasurement of Laddering Wave in Lossy Serpentine Delay Line
International Journal of Applied Science and Engineering 2006.4, 3: 291-295 Measurement of Laddering Wave in Lossy Serpentine Delay Line Fang-Lin Chao * Department of industrial Design, Chaoyang University
More informationPulse Width Modulation for On-chip Interconnects. Daniel Boijort Oskar Svanell
Pulse Width Modulation for On-chip Interconnects Daniel Boijort Oskar Svanell ISRN: LiTH-ISY-EX--05/3688--SE Linköping 2005 ii Philips Electronics N.V., 2005 Pulse Width Modulation for On-chip Interconnects
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationDigital Systems Power, Speed and Packages II CMPE 650
Speed VLSI focuses on propagation delay, in contrast to digital systems design which focuses on switching time: A B A B rise time propagation delay Faster switching times introduce problems independent
More informationImpact of Low-Impedance Substrate on Power Supply Integrity
Impact of Low-Impedance Substrate on Power Supply Integrity Rajendran Panda and Savithri Sundareswaran Motorola, Austin David Blaauw University of Michigan, Ann Arbor Editor s note: Although it is tempting
More informationSwitching (AC) Characteristics of MOS Inverters. Prof. MacDonald
Switching (AC) Characteristics of MOS Inverters Prof. MacDonald 1 MOS Inverters l Performance is inversely proportional to delay l Delay is time to raise (lower) voltage at nodes node voltage is changed
More informationCourse Content. Course Content. Course Format. Low Power VLSI System Design Lecture 1: Introduction. Course focus
Course Content Low Power VLSI System Design Lecture 1: Introduction Prof. R. Iris Bahar E September 6, 2017 Course focus low power and thermal-aware design digital design, from devices to architecture
More informationEECS 141: FALL 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you
More informationEECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations
EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)
More informationEECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies
EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)
More informationPROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS
PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high
More informationNovel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology
Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology 1 Mahesha NB #1 #1 Lecturer Department of Electronics & Communication Engineering, Rai Technology University nbmahesh512@gmail.com
More information! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements
EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams!
More informationHigh-speed Serial Interface
High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications
More informationSignal Integrity Modeling and Measurement of TSV in 3D IC
Signal Integrity Modeling and Measurement of TSV in 3D IC Joungho Kim KAIST joungho@ee.kaist.ac.kr 1 Contents 1) Introduction 2) 2.5D/3D Architectures with TSV and Interposer 3) Signal integrity, Channel
More informationCS4617 Computer Architecture
1/26 CS4617 Computer Architecture Lecture 2 Dr J Vaughan September 10, 2014 2/26 Amdahl s Law Speedup = Execution time for entire task without using enhancement Execution time for entire task using enhancement
More informationThrough-Silicon-Via Inductor: Is it Real or Just A Fantasy?
Through-Silicon-Via Inductor: Is it Real or Just A Fantasy? Umamaheswara Rao Tida 1 Cheng Zhuo 2 Yiyu Shi 1 1 ECE Department, Missouri University of Science and Technology 2 Intel Research, Hillsboro Outline
More informationLecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design)
Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design) Dr. Yingtao Jiang Department of Electrical and Computer Engineering University of Nevada Las
More informationDATASHEET HI-201HS. Features. Applications. Ordering Information. Pinout (Switches Shown For Logic 1 Input) High Speed, Quad SPST, CMOS Analog Switch
DATASHEET HI-21HS High Speed, Quad SPST, CMOS Analog Switch The HI-21HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit consists of
More informationECE 598 JS Lecture 13 Power Distribution
ECE 598 JS Lecture 13 Power Distribution Spring 2012 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationEE241 - Spring 2004 Advanced Digital Integrated Circuits. Announcements. Borivoje Nikolic. Lecture 15 Low-Power Design: Supply Voltage Scaling
EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 15 Low-Power Design: Supply Voltage Scaling Announcements Homework #2 due today Midterm project reports due next Thursday
More informationFEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES
6 Vol.11(1) March 1 FEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES P.J. Venter 1 and M. du Plessis 1 and Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical,
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More information1/19/2012. Timing in Asynchronous Circuits
Timing in Asynchronous Circuits 1 What do we mean by clock? The system clock for an integrated circuit is a voltage signal that pulses at a regular frequency. 1 0 Time The clock tells each stage of a circuit
More informationHI-201HS. Features. High Speed, Quad SPST, CMOS Analog Switch. Applications. Ordering Information. Pinout (Switches Shown For Logic 1 Input) FN3123.
HI-HS Data Sheet September 4 FN.4 High Speed, Quad SPST, CMOS Analog Switch The HI-HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit
More informationSemiconductor Technology Academic Research Center An RTL-to-GDS2 Design Methodology for Advanced System LSI
Semiconductor Technology Academic Research Center An RTL-to-GDS2 Design Methodology for Advanced System LSI Jan. 28. 2011 Nobuyuki Nishiguchi Semiconductor Technology Advanced Research Center (STARC) ASP-DAC
More informationECE 546 Introduction
ECE 546 Introduction Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Future System Needs and Functions Auto Digital
More informationCMD GHz GaN Low Noise Amplifier. Features. Functional Block Diagram. Description
Features Functional Block Diagram Ultra wideband performance Low noise figure High RF power survivablility Low current consumption Small die size Vdd Vgg2 RFOUT Description RFIN The CMD2 is a wideband
More informationHI-201HS. High Speed Quad SPST CMOS Analog Switch
SEMICONDUCTOR HI-HS December 99 Features Fast Switching Times, N = ns, FF = ns Low ON Resistance of Ω Pin Compatible with Standard HI- Wide Analog Voltage Range (±V Supplies) of ±V Low Charge Injection
More informationOn Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI
ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital
More informationPlane Crazy, Part 2 BEYOND DESIGN. by Barry Olney
by Barry Olney column BEYOND DESIGN Plane Crazy, Part 2 In my recent four-part series on stackup planning, I described the best configurations for various stackup requirements. But I did not have the opportunity
More informationTOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 DESCRIPTION The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and
More informationEECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline
EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy
More information