Interconnect. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
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1 Interconnect Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr (479)
2 Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
3 Wire Geometry Pitch = w + s Aspect ratio: AR = t/w Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny wires w s l t h 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 3
4 Layer Stack AMI 0.6 mm process has 3 metal layers M1 for within-cell routing M2 for vertical routing between cells M3 for horizontal routing between cells Modern processes use metal layers M1: thin, narrow (< 3l) High density cells Mid layers Thicker and wider, (density vs. speed) Top layers: thickest For VDD, GND, clk 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
![Stack [Moon08] 11/16/2017](/docs-images/94/121753415/images/5-3.jpg "CSCE/ELEG 4914: Advnaced")
5 Example Intel 90 nm Stack [Thompson02] Intel 45 nm Stack [Moon08] 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
6 Interconnect Modeling Current in a wire is analogous to current in a pipe Resistance: narrow size impedes flow Capacitance: trough under the leaky pipe must fill first Inductance: paddle wheel inertia opposes changes in flow rate Negligible for most wires 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 6
7 Lumped Element Models Wires are a distributed system Approximate with lumped element models N segments R R/N R/N R/N R/N C C/N C/N C/N C/N R R R/2 R/2 C L-model C/2 C/2 p-model C T-model 3-segment p-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment p-model for Elmore delay 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 7
8 Wire Resistance r = resistivity (W*m) R r l t w R l w R = sheet resistance (W/ ) is a dimensionless unit(!) w w Count number of squares R = R * (# of squares) w l l l t t 1 Rectangular Block R = R (L/W) W 4 Rectangular Blocks R = R (2L/2W) W = R (L/W) W 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 8
9 Choice of Metals Until 180 nm generation, most wires were aluminum Contemporary processes normally use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Metal Silver (Ag) 1.6 Copper (Cu) 1.7 Gold (Au) 2.2 Aluminum (Al) 2.8 Tungsten (W) 5.3 Titanium (Ti) 43.0 Bulk resistivity (mw cm) 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 9
10 Contacts Resistance Contacts and vias also have 2-20 W Use many contacts for lower R Many small contacts for current crowding around periphery 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 10
11 Copper Issues Copper wires diffusion barrier has high resistance Copper is also prone to dishing during polishing Effective resistance is higher R r l 2 t t t w t dish barrier barrier 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 11
12 Example Compute the sheet resistance of a 0.22 mm thick Au wire in a 65 nm process. Ignore dishing. R Ωm / W m Find the total resistance if the wire is mm wide and 1 mm long. Ignore the barrier layer m R 0.10 Ω/ m 800 W mm 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 12
13 Wire Capacitance Wire has capacitance per unit length To neighbors To layers above and below C total = C top + C bot + 2C adj s w layer n+1 h 2 C top t layer n h 1 C bot C adj layer n-1 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 13
14 Capacitance Trends Parallel plate equation: C = eoxa/d Wires are not parallel plates, but obey trends Increasing area (W, t) increases capacitance Increasing distance (s, h) decreases capacitance Dielectric constant eox = ke0 e0 = 8.85 x F/cm k = 3.9 for SiO2 Processes are starting to use low-k dielectrics k 3 (or less) as dielectrics use air pockets 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 14
15 Capacitance Formula Capacitance of a line without neighbors can be approximated as C tot w w t oxl h h h This empirical formula is accurate to 6% for AR < /16/2017 CSCE/ELEG 4914: Advnaced Digital Design 15
16 M2 Capacitance Data Typical dense wires have ~ 0.2 ff/mm Compare to 1-2 ff/mm for gate capacitance C total (af/mm) M1, M3 planes s = 320 s = 480 s = 640 s= Isolated s = 320 s = 480 s = 640 s= w (nm) 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 16
17 Diffusion & Polysilicon Diffusion capacitance is very high (1-2 ff/mm) Comparable to gate capacitance Diffusion also has high resistance Avoid using diffusion runners for wires! Polysilicon has lower C but high R Use for transistor gates Occasionally for very short wires between gates 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 17
18 Wire RC Delay and Power Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 1 mm wire. Assume a unit-sized inverter has R = 10 KΩ and C = 0.1 ff. tpd = (1000Ω)(100 ff) + ( Ω)( ff) = 281 ps Estimate the energy per unit length to send one bit of information (one rising and one falling transition) in a CMOS process with 1V Vdd. Assume wire capacitance is 0.2 ff/mm. E = (0.2 ff/mm)(1.0 V) 2 = 0.2 pj/bit/mm = 0.2 mw/gbps 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 18
19 Crosstalk A capacitor does not like to change its voltage instantaneously. A wire has high capacitance to its neighbor. When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. Called capacitive coupling or crosstalk. Crosstalk effects Noise on nonswitching wires Increased delay on switching wires 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 19
20 Crosstalk Delay Assume layers above and below on average are quiet Second terminal of capacitor can be ignored Model as Cgnd = Ctop + Cbot Effective Cadj depends on behavior of neighbors Miller effect C gnd A C adj B C gnd B DV C eff(a) MCF Constant V DD C gnd + C adj 1 Switching with A 0 C gnd 0 Switching opposite A 2V DD C gnd + 2 C adj 2 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 20
21 Crosstalk Noise Crosstalk causes noise on nonswitching wires If victim is floating: model as capacitive voltage divider C adj DVvictim D Cgnd v Cadj Aggressor V aggressor DV aggressor Victim C adj C gnd-v DV victim 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 21
22 Noise Implications So what if we have noise? If the noise is less than the noise margin, nothing happens Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes But glitches cause extra delay Also cause extra power from false transitions Dynamic logic never recovers from glitches Memories and other sensitive circuits also can produce the wrong answer 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 22
23 Wire Engineering Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom: Width Spacing Layer Shielding Delay (ns): RC/ Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) Pitch (nm) Wire Spacing (nm) vdd a 0 a 1 gnd a 2 a 3 vdd vdd a 0 gnd a 1 vdd a 2 gnd a 0 b 0 a 1 b 1 a 2 b 2 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 23
24 Repeaters R and C are proportional to l RC delay is proportional to l 2 Unacceptably great for long wires Break long wires into N shorter segments Drive each one with an inverter or buffer Wire Length: l Driver Receiver l/n N Segments Segment l/n l/n Driver Repeater Repeater Repeater Receiver 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 24
25 Repeater Design How many repeaters should we use? How large should each one be? Equivalent Circuit Wire length l/n Wire Capacitance Cw*l/N, Resistance Rw*l/N Inverter width W (nmos = W, pmos = 2W) Gate Capacitance C *W, Resistance R/W R w ln R/W C w l/2n C w l/2n C'W 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 25
26 Repeater Results Write equation for Elmore Delay Differentiate with respect to W and N Set equal to 0, solve t l N pd l W 2RC R C w w 2 2 RCw RC w RC R C w w ~40 ps/mm in 65 nm process 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 26
27 Repeater Energy Energy / length 1.87C w V DD 2 87% premium over unrepeated wires The extra power is consumed in the large repeaters If the repeaters are downsized for minimum EDP: Energy premium is only 30% Delay increases by 14% from min delay 11/16/2017 CSCE/ELEG 4914: Advnaced Digital Design 27
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