Lecture #2 Solving the Interconnect Problems in VLSI

Size: px
Start display at page:

Download "Lecture #2 Solving the Interconnect Problems in VLSI"

Transcription

1 Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology node was introduced How does this impact the design flow? Timing Closure problem IIT Madras - C.P. Ravikumar 2 1

2 Interconnect delays Source - ITRS IIT Madras - C.P. Ravikumar 3 Need for Communication-centric centric Design Flow Communication is THE most critical aspect affecting system performance Communication architecture consumes upto 50% of total on-chip power Ever increasing number of wires, repeaters, bus components (arbiters, bridges, decoders etc.) increases system cost Communication architecture design, customization, exploration, verification and implementation takes up the largest chunk of a design cycle Communication Architectures in today s complex systems significantly affect performance, power, cost and time-to-market! significantly affect performance, IIT Madras - C.P. power, Ravikumar cost and time-to-market! Sudeep Pasricha & Nikil Dutt 4 2

3 Cu Al 1.72 x 10-8 Ωm 2.82 x 10-8 Ωm Solutions Material with better ρ Moving to copper interconnect Trenches are created in the underlying silicon oxide insulating layer where the metal is desired. A thick coating of copper deposited overfills the trenches Chemical-mechanical Polishing used to remove the copper to the level of the top of the insulating layer Barrier metal needed to prevent spreading IIT Madras - C.P. Ravikumar 5 Interconnect Reliability Metal Migration (EM) Can result in long-term failure of interconnects Reliability problem in integrated circuits Copper is better than Aluminum IIT Madras - C.P. Ravikumar 6 3

4 Increase metal thickness Solutions Reduce interconnect resistance What side effects does this cause? R = ρl HW IIT Madras - C.P. Ravikumar 7 Solutions to Crosstalk Problem: Reduce parasitic capacitance Low-k Dielectric Silicon Dioxide has a relative permittivity of 3.9 Materials research has yielded dielectrics with lower permittivity Flourine doped SiO Carbon doped SiO Crosstalk analysis Crosstalk Delay and Crosstalk Failure Increase metal separation (selectively) Crosstalk aware placement & routing IIT Madras - C.P. Ravikumar 8 4

5 Interconnect Estimation Logic Synthesis tools need to estimate interconnect lengths and wire delays Statistical Wire Load Model (WLM) Physical Synthesis tools perform placement and routing concurrently with synthesis IIT Madras - C.P. Ravikumar 9 Interconnect Delay Calculation Lumped and Distributed Delay Models IIT Madras - C.P. Ravikumar 10 5

6 Elmore Delay Model V in R 1 R R i-1 i-1 R i i R N-1 N-1 R N N V out C 1 C 2 C i-1 C i C N-1 C N τ N = N i= 1 R N i j= i C j = N i= 1 C i i j= 1 R j IIT Madras - C.P. Ravikumar 11 Example Assume N segments, each with resistance r and capacitance c The Elmore Delay can be further extended for interconnects with tree topology IIT Madras - C.P. Ravikumar 12 6

7 Elmore Delay for RC Tree Delay at a node j = Σ k (C k R jk ) R jk is the sum of all resistances that are common to the path from the source to node j and the path from source to node k Delay at node 1 = C 1 (R 1 ) + C 2 (R 1 ) + C 3 (R 1 ) Delay at node 2 = C 1 (R 1 ) + C 2 (R 1 +R 2 ) + C 3 (R 1 ) Delay at node 3 = C 1 (R 1 ) + C 2 (R 1 ) + C 3 (R 1 +R 3 ) IIT Madras - C.P. Ravikumar 13 When should inductance be considered? Length criteria for including inductance in interconnect model IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 14 7

8 Reducing Interconnect Delay Repeater Insertion Where should the buffers be inserted? What are the sizes of the buffers? IIT Madras - C.P. Ravikumar 15 Interconnect Delay with repeaters Consider a wire of length L, divided into N sections Assume that there are N repeaters, one at the beginning of each section Assume that the W/L ratio for a unit-sized driver is β Assume that all drivers are of size M Model for any section must include Self-resistance of the repeater Self-capacitance of the repeater π-model of the Interconnect segment of length L/N Load capacitance presented by the subsequent repeater IIT Madras - C.P. Ravikumar 16 8

9 RC-model for one segment R 1 = R d /M R 2 = R int L/N C 1 = C d M (1+β) + C int L/(2N) C 2 = C g M (1+β) + C int L/(2N) Elmore Delay at the output of the segment is: t segment = R 1 C 1 + (R 1 +R 2 )C 2 Total delay of the wire with repeaters = N t segment Differentiate the total delay expression w.r.t. N and set it to 0 ; solve for N to get N opt Differentiate the total delay expression w.r.t. M and set it to 0; solve for M to get M opt IIT Madras - C.P. Ravikumar 17 Signal Routing Synchronous digital circuits that use edge-triggered flip-flops Concept of setup delay Period of the clock = T T > t clk-q of launch flop + Path delay from Q launch to D capture + t setup of capture flop Path Delay in deep submicron technologies depends on Gate Delay (which is a function of P, V, T) Interconnect Delay IIT Madras - C.P. Ravikumar 18 9

10 Logic Synthesis and Physical Design Before 130nm technology, it was possible to separate logic synthesis and physical design Interconnect delays were not as big a component as gate delay before 180nm Estimating interconnect delay through statistical wireload model was reasonably accurate in 180nm technology Timing Closure problems in 130nm technology and beyond Unable to predict interconnect delays accurately without knowledge of placement and routing information Physical Synthesis performs logic synthesis + physical design simultaneously tools are more complex IIT Madras - C.P. Ravikumar 19 Performance-directed Placement and Routing Delays estimated in logic synthesis can be fed as constraints to physical design tools Early physical design tools mainly focussed on minimizing TOTAL wire length There were constraints on routing congestion Placement and routing tools today accept timing constraints IIT Madras - C.P. Ravikumar 20 10

11 Routing Trees 10 units of wire A multiple-pin net (wire) is routed as a tree Minimum-length Rectilinear Spanning Tree Create an MST using Euclidean distance as a measure Convert the edges to Manhattan routes Minimum-length Rectilinear Steiner Tree Introduce Steiner points Example shows a 4-pin net E.G. One gate driving 3 other gates IIT Madras - C.P. Ravikumar 21 8 units of wire Wireload model Get an estimate of wirelength at logic synthesis stage Model wire-length as a function of fan-out Statistical Wireload model Collect chip data and create a correlation between fanout and wirelength IIT Madras - C.P. Ravikumar 22 11

12 Driver Sizing Transistor sizing techniques aim to lower delay Wider transistors have a few advantages but also several disadvantages + produce more current + reduce charge time of load capacitance have greater physical area have larger gate capacitance increased circuit area and power IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 23 Wire Sizing Width of an interconnect affects the power characteristics and propagation delay Consider a CMOS inverter driving an RC interconnect line Simple first order model of delay IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 24 12

13 Wire Sizing Increasing the driver transistor width reduces R tr decreasing the circuit delay trading off circuit power and area for higher speed Increasing the width of the interconnect to reduce R int does not significantly reduce the delay caused by the RC interconnect impedance since decrease in wire resistance is offset by increase in wire capacitance IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 25 Wire Sizing Dynamic power increases with width since line capacitance is greater As line inductance-to-resistance ratio increases with wider lines, short-circuit power decreases due to reduction in signal transition time IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 26 13

14 3-D ICs With shorter interconnects in 3D ICs, switching energy and cycle time are expected to be reduced Take advantage of multiple layers in routing critical paths IIT Madras - C.P. Ravikumar 27 Types of interconnects Signal carriers Carry data and control signals Clock carriers Power and Ground IIT Madras - C.P. Ravikumar 28 14

15 Clock Tree Construction Synchronous circuits require that (ideally) all flipflops toggle at the same time Interconnect Delays along the clock line result in clock skew Clocks are often designed as H-tree to balance the skew from source to sinks T > skew + t clk-q of launch flop + Path delay from Q launch to D capture + t setup of capture flop When number of IP increases, maintaining the synchronous paradigm is a challenge Globally Asynchronous, Locally Synchronous IIT Madras - C.P. Ravikumar 29 Signal Carriers Point-to-point connections One source of data and one sink Sometimes, we may have multiple sources of data and multiple sinks Example multiple CPUs / multiple memories Bus is a way to share data paths Reduces interconnect area As we increase the number of sources/sinks, communication latencies increase IIT Madras - C.P. Ravikumar 30 15

16 Bus Terminology IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 31 Bus Terminology Master (or Initiator)? IP component that initiates a read or write data transfer Slave (or Target)? IP component that does not initiate transfers and only responds to incoming transfer requests Arbiter? Controls access to the shared bus? Uses arbitration scheme to select master to grant access to bus Decoder? Determines which component a transfer is intended for Bridge? Connects two busses? Acts as slave on one side and master on the other IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 32 16

17 Bus Physical Structure tri-state buffer based bidirectional signals Commonly used in off-chip/backplane buses + take up fewer wires, smaller area footprint - higher power consumption, higher delay, hard to debug IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 33 Bus Physical Structure MUX based signals Separate read, write channels IIT Madras - C.P. Ravikumar Sudeep Pasricha & Nikil Dutt 34 17

18 Bus interconnects Routing congestion Example a single controller for a large number of data path elements Higher Bus capacitance implies higher bus power and delay Crosstalk may result in data errors Data encoding techniques exist to reduce such errors and the switching activity on the bus lines IIT Madras - C.P. Ravikumar 35 Bus crosstalk Concept of a victim and an aggressor In a bus with multiple wires, a single wire may have multiple aggressors Shielding can eliminate the crosstalk between two wires Extra area An entire metal layer is sometimes used in between two metal layers to shield wires in the two layers from crosstalk Encoding of data can be used to achieve a similar effect IIT Madras - C.P. Ravikumar 36 18

Switching (AC) Characteristics of MOS Inverters. Prof. MacDonald

Switching (AC) Characteristics of MOS Inverters. Prof. MacDonald Switching (AC) Characteristics of MOS Inverters Prof. MacDonald 1 MOS Inverters l Performance is inversely proportional to delay l Delay is time to raise (lower) voltage at nodes node voltage is changed

More information

Chapter 4. Problems. 1 Chapter 4 Problem Set

Chapter 4. Problems. 1 Chapter 4 Problem Set 1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock network (between the nodes) is 5 mm long, 3 µm wide, and is implemented

More information

2.5D & 3D Package Signal Integrity A Paradigm Shift

2.5D & 3D Package Signal Integrity A Paradigm Shift 2.5D & 3D Package Signal Integrity A Paradigm Shift Nozad Karim Technology & Platform Development November, 2011 Enabling a Microelectronic World Content Traditional package signal integrity vs. 2.5D/3D

More information

EE434 ASIC & Digital Systems. Partha Pande School of EECS Washington State University

EE434 ASIC & Digital Systems. Partha Pande School of EECS Washington State University EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 11 Physical Design Issues Interconnect Scaling Effects Dense multilayer metal increases coupling

More information

Lecture 13: Interconnects in CMOS Technology

Lecture 13: Interconnects in CMOS Technology Lecture 13: Interconnects in CMOS Technology Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/18/18 VLSI-1 Class Notes Introduction Chips are mostly made of wires

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

Microcircuit Electrical Issues

Microcircuit Electrical Issues Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the

More information

Interconnect. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

Interconnect. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. Interconnect Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Introduction Chips are mostly made of wires called

More information

UNIT-II LOW POWER VLSI DESIGN APPROACHES

UNIT-II LOW POWER VLSI DESIGN APPROACHES UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.

More information

Interconnect/Via CONCORDIA VLSI DESIGN LAB

Interconnect/Via CONCORDIA VLSI DESIGN LAB Interconnect/Via 1 Delay of Devices and Interconnect 2 Reduction of the feature size Increase in the influence of the interconnect delay on system performance Skew The difference in the arrival times of

More information

Module -18 Flip flops

Module -18 Flip flops 1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip

More information

Timing analysis can be done right after synthesis. But it can only be accurately done when layout is available

Timing analysis can be done right after synthesis. But it can only be accurately done when layout is available Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 11: Wires, Elmore Delay

EE115C Winter 2017 Digital Electronic Circuits. Lecture 11: Wires, Elmore Delay EE115C Winter 2017 Digital Electronic Circuits Lecture 11: Wires, Elmore Delay The Wire transmitters receivers schematics physical EE115C Winter 2017 2 Interconnect Impact on Chip EE115C Winter 2017 3

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

Managing Cross-talk Noise

Managing Cross-talk Noise Managing Cross-talk Noise Rajendran Panda Motorola Inc., Austin, TX Advanced Tools Organization Central in-house CAD tool development and support organization catering to the needs of all design teams

More information

Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design)

Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design) Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design) Dr. Yingtao Jiang Department of Electrical and Computer Engineering University of Nevada Las

More information

A Survey of the Low Power Design Techniques at the Circuit Level

A Survey of the Low Power Design Techniques at the Circuit Level A Survey of the Low Power Design Techniques at the Circuit Level Hari Krishna B Assistant Professor, Department of Electronics and Communication Engineering, Vagdevi Engineering College, Warangal, India

More information

Signal Integrity Management in an SoC Physical Design Flow

Signal Integrity Management in an SoC Physical Design Flow Signal Integrity Management in an SoC Physical Design Flow Murat Becer Ravi Vaidyanathan Chanhee Oh Rajendran Panda Motorola, Inc., Austin, TX Presenter: Rajendran Panda Talk Outline Functional and Delay

More information

Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits

Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits Santosh Khasanvis, Mostafizur Rahman, Mingyu Li, Jiajun Shi, and Csaba Andras Moritz* Dept. of Electrical and Computer Engineering,

More information

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy

More information

Digital Design and System Implementation. Overview of Physical Implementations

Digital Design and System Implementation. Overview of Physical Implementations Digital Design and System Implementation Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops

More information

Programmable Interconnect. CPE/EE 428, CPE 528: Session #13. Actel Programmable Interconnect. Actel Programmable Interconnect

Programmable Interconnect. CPE/EE 428, CPE 528: Session #13. Actel Programmable Interconnect. Actel Programmable Interconnect Programmable Interconnect CPE/EE 428, CPE 528: Session #13 Department of Electrical and Computer Engineering University of Alabama in Huntsville In addition to programmable cells, programmable ASICs must

More information

Advanced Digital Design

Advanced Digital Design Advanced Digital Design Introduction & Motivation by A. Steininger and M. Delvai Vienna University of Technology Outline Challenges in Digital Design The Role of Time in the Design The Fundamental Design

More information

VLSI Design: Challenges and Promise

VLSI Design: Challenges and Promise VLSI Design: Challenges and Promise An Overview Dinesh Sharma Electronic Systems, EE Department IIT Bombay, Mumbai September 11, 2015 Impact of Microelectronics Microelectronics has transformed life styles

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements

More information

Deep Submicron Interconnect. 0.18um vs. 013um Interconnect

Deep Submicron Interconnect. 0.18um vs. 013um Interconnect Deep Submicron Interconnect R. Dept. of ECE University of British Columbia res@ece.ubc.ca 0.18um vs. 013um Interconnect 0.18µm 5-layer Al Metal Process 0.13µm 8-layer Cu Metal Process 1 Interconnect Scaling

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 CPLD / FPGA CPLD Interconnection of several PLD blocks with Programmable interconnect on a single chip Logic blocks executes

More information

PROGRAMMABLE ASIC INTERCONNECT

PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC INTERCONNECT The structure and complexity of the interconnect is largely determined by the programming technology and the architecture of the basic logic cell The first programmable ASICs

More information

CROSS-COUPLING capacitance and inductance have. Performance Optimization of Critical Nets Through Active Shielding

CROSS-COUPLING capacitance and inductance have. Performance Optimization of Critical Nets Through Active Shielding IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 51, NO. 12, DECEMBER 2004 2417 Performance Optimization of Critical Nets Through Active Shielding Himanshu Kaul, Student Member, IEEE,

More information

RECENT technology trends have lead to an increase in

RECENT technology trends have lead to an increase in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1581 Noise Analysis Methodology for Partially Depleted SOI Circuits Mini Nanua and David Blaauw Abstract In partially depleted silicon-on-insulator

More information

EDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems

EDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems EDA Challenges for Low Power Design Anand Iyer, Cadence Design Systems Agenda Introduction ti LP techniques in detail Challenges to low power techniques Guidelines for choosing various techniques Why is

More information

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.

More information

! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.

! Review: Sequential MOS Logic.  SR Latch.  D-Latch. ! Timing Hazards. ! Dynamic Logic.  Domino Logic. ! Charge Sharing Setup. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "

More information

Timing Issues in FPGA Synchronous Circuit Design

Timing Issues in FPGA Synchronous Circuit Design ECE 428 Programmable ASIC Design Timing Issues in FPGA Synchronous Circuit Design Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 1-1 FPGA Design Flow Schematic capture HDL

More information

DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N

DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical

More information

Low-Power Digital CMOS Design: A Survey

Low-Power Digital CMOS Design: A Survey Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with

More information

LSI and Circuit Technologies for the SX-8 Supercomputer

LSI and Circuit Technologies for the SX-8 Supercomputer LSI and Circuit Technologies for the SX-8 Supercomputer By Jun INASAKA,* Toshio TANAHASHI,* Hideaki KOBAYASHI,* Toshihiro KATOH,* Mikihiro KAJITA* and Naoya NAKAYAMA This paper describes the LSI and circuit

More information

Fan in: The number of inputs of a logic gate can handle.

Fan in: The number of inputs of a logic gate can handle. Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

CS250 VLSI Systems Design. Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing

CS250 VLSI Systems Design. Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing CS250 VLSI Systems Design Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing Fall 2010 Krste Asanovic, John Wawrzynek with John Lazzaro and Yunsup Lee (TA) What do Computer

More information

Computer Architecture (TT 2012)

Computer Architecture (TT 2012) Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture

More information

Clock Tree 101. by Linda Lua

Clock Tree 101. by Linda Lua Tree 101 by Linda Lua Table of Contents I. What is a Tree? II. III. Tree Components I. Crystals and Crystal Oscillators II. Generators III. Buffers IV. Attenuators versus Crystal IV. Free-running versus

More information

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative

More information

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

Pulse Width Modulation for On-chip Interconnects. Daniel Boijort Oskar Svanell

Pulse Width Modulation for On-chip Interconnects. Daniel Boijort Oskar Svanell Pulse Width Modulation for On-chip Interconnects Daniel Boijort Oskar Svanell ISRN: LiTH-ISY-EX--05/3688--SE Linköping 2005 ii Philips Electronics N.V., 2005 Pulse Width Modulation for On-chip Interconnects

More information

Lecture 02: Digital Logic Review

Lecture 02: Digital Logic Review CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:

More information

Design of low-power, high performance flip-flops

Design of low-power, high performance flip-flops Int. Journal of Applied Sciences and Engineering Research, Vol. 3, Issue 4, 2014 www.ijaser.com 2014 by the authors Licensee IJASER- Under Creative Commons License 3.0 editorial@ijaser.com Research article

More information

Lecture 11: Clocking

Lecture 11: Clocking High Speed CMOS VLSI Design Lecture 11: Clocking (c) 1997 David Harris 1.0 Introduction We have seen that generating and distributing clocks with little skew is essential to high speed circuit design.

More information

Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting

Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting C. Guardiani, C. Forzan, B. Franzini, D. Pandini Adanced Research, Central R&D, DAIS,

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f

More information

Impedance Matching: Terminations

Impedance Matching: Terminations by Barry Olney IN-CIRCUIT DESIGN PTY LTD AUSTRALIA column BEYOND DESIGN Impedance Matching: Terminations The impedance of the trace is extremely important, as any mismatch along the transmission path will

More information

Lecture 4&5 CMOS Circuits

Lecture 4&5 CMOS Circuits Lecture 4&5 CMOS Circuits Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese566/ Worst-Case V OL 2 3 Outline Combinational Logic (Delay Analysis) Sequential Circuits

More information

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Lecture 01: the big picture Course objective Brief tour of IC physical design

More information

EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector

EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1 Table

More information

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute.  From state elements ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

More information

A Novel Low-Power Scan Design Technique Using Supply Gating

A Novel Low-Power Scan Design Technique Using Supply Gating A Novel Low-Power Scan Design Technique Using Supply Gating S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,

More information

LSI Design Flow Development for Advanced Technology

LSI Design Flow Development for Advanced Technology LSI Design Flow Development for Advanced Technology Atsushi Tsuchiya LSIs that adopt advanced technologies, as represented by imaging LSIs, now contain 30 million or more logic gates and the scale is beginning

More information

IFSIN. WEB PAGE Fall ://weble.upc.es/ifsin/

IFSIN. WEB PAGE   Fall ://weble.upc.es/ifsin/ IFSIN IMPLEMENTACIÓ FÍSICA DE SISTEMES INTEGRATS NANOMÈTRICS IMPLEMENTACIÓN N FÍSICA F DE SISTEMAS INTEGRADOS NANOMÉTRICOS PHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS Fall 2008 Prof. Xavier

More information

Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect

Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Introduction - So far, have considered transistor-based logic in the face of technology scaling - Interconnect effects are also of concern

More information

Chapter 1 Introduction

Chapter 1 Introduction Chapter 1 Introduction 1.1 Introduction There are many possible facts because of which the power efficiency is becoming important consideration. The most portable systems used in recent era, which are

More information

Worst Case RLC Noise with Timing Window Constraints

Worst Case RLC Noise with Timing Window Constraints Worst Case RLC Noise with Timing Window Constraints Jun Chen Electrical Engineering Department University of California, Los Angeles jchen@ee.ucla.edu Lei He Electrical Engineering Department University

More information

EE141- Spring 2004 Digital Integrated Circuits

EE141- Spring 2004 Digital Integrated Circuits EE141- Spring 2004 Digital Integrated Circuits Lecture 27 Power distribution Resistive interconnect 1 Administrative Stuff Make-up lecture on Monday 4-5:30pm Special office hours of Prof. Rabaey today

More information

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University. EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL

More information

LOW-POWER SOFTWARE-DEFINED RADIO DESIGN USING FPGAS

LOW-POWER SOFTWARE-DEFINED RADIO DESIGN USING FPGAS LOW-POWER SOFTWARE-DEFINED RADIO DESIGN USING FPGAS Charlie Jenkins, (Altera Corporation San Jose, California, USA; chjenkin@altera.com) Paul Ekas, (Altera Corporation San Jose, California, USA; pekas@altera.com)

More information

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals

More information

Exploring the Basics of AC Scan

Exploring the Basics of AC Scan Page 1 of 8 Exploring the Basics of AC Scan by Alfred L. Crouch, Inovys This in-depth discussion of scan-based testing explores the benefits, implementation, and possible problems of AC scan. Today s large,

More information

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 77-81 International Research Publication House http://www.irphouse.com Noise Tolerance Dynamic CMOS Logic

More information

Policy-Based RTL Design

Policy-Based RTL Design Policy-Based RTL Design Bhanu Kapoor and Bernard Murphy bkapoor@atrenta.com Atrenta, Inc., 2001 Gateway Pl. 440W San Jose, CA 95110 Abstract achieving the desired goals. We present a new methodology to

More information

Variation-Aware Design for Nanometer Generation LSI

Variation-Aware Design for Nanometer Generation LSI HIRATA Morihisa, SHIMIZU Takashi, YAMADA Kenta Abstract Advancement in the microfabrication of semiconductor chips has made the variations and layout-dependent fluctuations of transistor characteristics

More information

Bus Serialization for Reducing Power Consumption

Bus Serialization for Reducing Power Consumption Regular Paper Bus Serialization for Reducing Power Consumption Naoya Hatta, 1 Niko Demus Barli, 2 Chitaka Iwama, 3 Luong Dinh Hung, 1 Daisuke Tashiro, 4 Shuichi Sakai 1 and Hidehiko Tanaka 5 On-chip interconnects

More information

Signal Integrity for Gigascale SOC Design. Professor Lei He ECE Department University of Wisconsin, Madison

Signal Integrity for Gigascale SOC Design. Professor Lei He ECE Department University of Wisconsin, Madison Signal Integrity for Gigascale SOC Design Professor Lei He ECE Department University of Wisconsin, Madison he@ece.wisc.edu http://eda.ece.wisc.edu Outline Capacitive noise Technology trends Capacitance

More information

! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.

! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology.  Gate choice, logical optimization.  Fanin, fanout, Serial vs. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!

More information

EECS 141: FALL 98 FINAL

EECS 141: FALL 98 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you

More information

Digital Systems Power, Speed and Packages II CMPE 650

Digital Systems Power, Speed and Packages II CMPE 650 Speed VLSI focuses on propagation delay, in contrast to digital systems design which focuses on switching time: A B A B rise time propagation delay Faster switching times introduce problems independent

More information

ECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh

ECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh NMOS-to-PMOS ratio,pmos are made β times larger than NMOS Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing

More information

FEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES

FEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES 6 Vol.11(1) March 1 FEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES P.J. Venter 1 and M. du Plessis 1 and Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical,

More information

Methods for Reducing the Activity Switching Factor

Methods for Reducing the Activity Switching Factor International Journal of Engineering Research and Development e-issn: 2278-67X, p-issn: 2278-8X, www.ijerd.com Volume, Issue 3 (March 25), PP.7-25 Antony Johnson Chenginimattom, Don P John M.Tech Student,

More information

A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication

A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication Peggy B. McGee, Melinda Y. Agyekum, Moustafa M. Mohamed and Steven M. Nowick {pmcgee, melinda, mmohamed,

More information

Trends and Challenges in VLSI Technology Scaling Towards 100nm

Trends and Challenges in VLSI Technology Scaling Towards 100nm Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends

More information

Mohit Arora. The Art of Hardware Architecture. Design Methods and Techniques. for Digital Circuits. Springer

Mohit Arora. The Art of Hardware Architecture. Design Methods and Techniques. for Digital Circuits. Springer Mohit Arora The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits Springer Contents 1 The World of Metastability 1 1.1 Introduction 1 1.2 Theory of Metastability 1 1.3 Metastability

More information

DDR4 memory interface: Solving PCB design challenges

DDR4 memory interface: Solving PCB design challenges DDR4 memory interface: Solving PCB design challenges Chang Fei Yee - July 23, 2014 Introduction DDR SDRAM technology has reached its 4th generation. The DDR4 SDRAM interface achieves a maximum data rate

More information

DATASHEET CADENCE QRC EXTRACTION

DATASHEET CADENCE QRC EXTRACTION DATASHEET Cadence QRC Etraction, the industry s premier 3D fullchip parasitic etractor that is independent of design style or flow, is a fast and accurate RLCK etraction solution used during design implementation

More information

EE141-Spring 2007 Digital Integrated Circuits

EE141-Spring 2007 Digital Integrated Circuits EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon

More information

White Paper Stratix III Programmable Power

White Paper Stratix III Programmable Power Introduction White Paper Stratix III Programmable Power Traditionally, digital logic has not consumed significant static power, but this has changed with very small process nodes. Leakage current in digital

More information

High-speed Serial Interface

High-speed Serial Interface High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications

More information

Contents 1 Introduction 2 MOS Fabrication Technology

Contents 1 Introduction 2 MOS Fabrication Technology Contents 1 Introduction... 1 1.1 Introduction... 1 1.2 Historical Background [1]... 2 1.3 Why Low Power? [2]... 7 1.4 Sources of Power Dissipations [3]... 9 1.4.1 Dynamic Power... 10 1.4.2 Static Power...

More information

Performance Comparison of Various Clock Gating Techniques

Performance Comparison of Various Clock Gating Techniques IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 1, Ver. II (Jan - Feb. 2015), PP 15-20 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Performance Comparison of Various

More information

A Comparative Study of Π and Split R-Π Model for the CMOS Driver Receiver Pair for Low Energy On-Chip Interconnects

A Comparative Study of Π and Split R-Π Model for the CMOS Driver Receiver Pair for Low Energy On-Chip Interconnects International Journal of Scientific and Research Publications, Volume 3, Issue 9, September 2013 1 A Comparative Study of Π and Split R-Π Model for the CMOS Driver Receiver Pair for Low Energy On-Chip

More information

Substrate Coupling in RF Analog/Mixed Signal IC Design: A Review

Substrate Coupling in RF Analog/Mixed Signal IC Design: A Review Substrate Coupling in RF Analog/Mixed Signal IC Design: A Review Ashish C Vora, Graduate Student, Rochester Institute of Technology, Rochester, NY, USA. Abstract : Digital switching noise coupled into

More information

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy School of Electrical and Computer Engineering, Purdue University,

More information

EECS 427 Lecture 21: Design for Test (DFT) Reminders

EECS 427 Lecture 21: Design for Test (DFT) Reminders EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final

More information

Microcontroller Systems. ELET 3232 Topic 13: Load Analysis

Microcontroller Systems. ELET 3232 Topic 13: Load Analysis Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission

More information

High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers

High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency

More information

Digital Design: An Embedded Systems Approach Using VHDL

Digital Design: An Embedded Systems Approach Using VHDL Digital Design: An Embedded Systems Approach Using Chapter 6 Implementation Fabrics Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using, by Peter J. Ashenden, published

More information

Interconnect-Power Dissipation in a Microprocessor

Interconnect-Power Dissipation in a Microprocessor 4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition

More information

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R RW 6 W 1 C C 3 D R t 1 R R t 2 R R t

More information

Source Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication

Source Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication Source Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication Abstract: Double-edged pulse width modulation (DPWM) is less sensitive to frequency-dependent losses in electrical

More information

Chapter 3 Chip Planning

Chapter 3 Chip Planning Chapter 3 Chip Planning 3.1 Introduction to Floorplanning 3. Optimization Goals in Floorplanning 3.3 Terminology 3.4 Floorplan Representations 3.4.1 Floorplan to a Constraint-Graph Pair 3.4. Floorplan

More information