Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI s

Transcription

1 Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI s author Dr. Takayasu Sakurai Semiconductor Device Engnieering Laboratory, Toshiba Corporation, Tokoyo, Japan IEEE Transaction on Electron Devices, 1993, 40, presenter Moumita Jana 28 th February 2012

2 Introduction Interconnection delay, coupling, and crosstalk are important as the feature size of the line is miniaturized In modern VLSI design wires have become narrower resulting higher resistance Closely placed wires result capacitive coupling When one wire switches, it tends to bring its neighbor along with it on account of capacitive coupling and results crosstalk The crosstalk becomes eminent when mixed CMOS/ECL signals are used on a chip 2

3 RC Delay of Aluminum Interconnection An aluminum interconnection of 20 mm length and 0.5 mm width shows RC delay of 3 ns, assuming that its sheet resistance of 35 mω and capacitance of 0.11 ff/µm W h CMOS VLSI Design: A Circuit and System Perspective. Neil H.E. Weste and David M. Harris, 4 th ed This delay is about 40 times longer than an inverter switching time of same generation This delay is also about 5 times longer than an optimized buffer delay to drive the pure capacitance of the interconnection 3

4 Model of a RC System A Model and notation of an interconnection driven by a resistive voltage source and loaded with capacitor A) Circuit B) model of an RC interconnection Differential equation Using Heaviside s expansion theorem: The voltage waveform can be expressed as: (5) 4

5 Comparison Between Exact Values of K 1, σ 1 with Their Simple Formulas Exact value of K 1 vs. simple formula Exact value of σ 1 vs. simple formula The relative errors are less than 3% for K 1 and less than 4% for σ 1 5

6 Delay of RC Interconnection The delay t v is from t=0 to the time when the normalized voltage at the end point reaches v=v/e (6) Voltage waveform of distributed RC line Exact delay vs. simple formula The error is less than 3.5% of RC Elmore delay for a distributed RC line is not as accurate as (6) The transition time expression is 6

7 Coupling capacitance for three lines Coupling Capacitance Coupling capacitance for two lines Total capacitance for three lines Total capacitance for two lines Capacitance for single line: The relative errors of the formulas for C 3 and C 2 are less than 10% for 0.3<(T/H), (W/H)<10 and 0.5<(S/H)<10 The relative error of the formula for C 1 is less than 6% for 0.3<(T/H), (W/H)<30 7

8 Optimum Linewidth Two outer lines are driven by an inverted signal of the center line Center line feels an effective capacitance (C 20 +4C 21 ) RC delay in arbitrary unit becomes (C 20 +4C 21 )/(W/H) RC delay vs. linewidth Optimum linewidth vs. pitch of lines Optimum width is about half the pitch as long as the pitch is less than 4X the height 8

9 Relationship: Total & RC Interconnection Delay The total delay D TOT is the sum buffering delay D BUF and the RC interconnection delay Minimizing D TOT in terms of r t For 0.5 µm CMOS technology total delay reduced to The RC interconnection delay surmounts the buffering delay 9

10 RC Delay in a Bus Structure H, T, W, and S are assumed to be 1 µm in 1990 Sheet resistance is assumed 30 mω Feature size is scaled exponentially from 1 µm in 1990 to 0.25 µm in 2000 Chip side length is increased exponentially from 10 mm in 1990 to 25 mm in 2000 The unscaled interconnection scheme is the most attractive 10

11 Voltage Waveforms of Two Parallel RC Lines The basic differential equations which govern two capacitively coupled RC lines Simplified differential equation in terms of V + and V - 11

12 Closed-Form Expression for Voltage Waveform Closed-form expressions for the voltage waveform Simulated and calculated waveforms of capacitively coupled RC lines 12

13 Noise height induced by capacitive crosstalk Noise height V p is: For R t1 is zero and R t2 is V p becomes The maximum error is less than 3% of E 1 13

14 Conclusion Practical expressions are derived for RC interconnection delay and voltage waveform Simple formulas for coupling capacitances are proposed with error less than 15% for the practical range of parameters The optimum width to minimize a bus RC delay is calculated using those formulas RC delay for unscaled interconnection is effective in reducing RC delay Expression for peak-noise height for RC interconnection system is given The crosstalk effect is estimated by using the crosstalk formulas in mixed-signal VLSI design 14

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