Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing

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1 Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing Nestoras Tzartzanis and Bill Athas nestoras@isiedu, athas@isiedu Information Sciences Institute University of Southern California

2 Outline The problem Standard approaches The idea of energy recovery and adiabatic charging Driver experiment Clock-powered logic Conclusions

3 RF Decoder Address RF Word Lines Write Dec Read Dec 0 Read Dec 1 Register File The Problem Bypass from MEM Stage / Write Back Bypass from EXE Stage / A-Bus Source Op FU Res ALU Comp Unit Shifter D in -Bus Control Signals Control Unit Constant I-Bus / Instruction Register Bus D out -Bus Indexed Address PC Unit Return Address PC-Bus Processors contain some registers, a little bit of logic, and lots of long wires Problem: driving high-capacitance interconnects in an energyefficient way High- Capacitance Nets

4 A Basic Approach The basic approach in CMOS: Use reduced-voltage drivers and low-to-high voltage converters D in V dd V ddl C Voltage Converter V dd D out low-swing signal high-swing signal Approach is limited by threshold voltages

5 Inverters as Low-Swing Drivers An inverter is used as a driver A dual-rail-input low-to-high voltage converter is used D in D in x l V ddl x p D V ddl D 150 ff x l x p 150 ff D in V ddl Driver 268 µm D out 86 µm HSPICE simulations for HP 05 µm, 33 V process

6 Energy vs Delay for the Inverter V dd is set to 33 V V ddl is varied from 33 to 11 V Record energy for driving the load and delay through the converter 33 V 10 0 Energy (pj) 12 V Delay (ns) Voltage reduction is limited by the threshold voltage of the converter Delay rapidly increases as V ddl is scaled (36 ns for V ddl = 11 V)

7 Simple Improvement A modified inverter is used as a driver V ddl 268 µm 86 µm V Inverter Modified Inv D in 86 µm D in Dout Energy (pj) V 12 V Modified Inverter Delay (ns) Reduces delay for low voltages Minimum energy dissipation is still limited by the threshold voltage of the converter

8 Standard CMOS V C V R p R n C Standard CMOS: E = CV 2 Possible ONLY to reduce voltage

9 Adiabatic Charging ~ C R ~ C V 0 T Adiabatic CMOS: E = CV RC 2 T Reduce dissipation by reducing voltage AND increasing the energy transport time

10 An Adiabatic Driver: The Energy-Recovery Latch Output node is clock powered Energy is injected and recovered through the same path Based on bootstrapped clocked buffer [Glasser & Dobberpuhl 1985] ϕ L I 1 V iso D in D Latch inl M 1 the boot node (bn) Adiabatic V ϕ path M 2 V 0 out T Minimizes R for given boot-node capacitance Operates with two non-overlapping clock phases ϕ D M 3 C V ϕ 0 ϕ L V bn V out ϕ D

11 Model for On-Resistance of Bootstrapped Transistor Bootstrap nfet on-resistance was analytically modeled for the case of linear-ramp charging Resistance (Ω) Supply Voltage V dd (V) Model HSPICE Clock Voltage Swing V ϕ (V) Analytical model can be used for sizing bootstrap transistor depending on load capacitance and switching time

12 Driver Experiment Set-Up Purpose: to experimentally determine when increasing the switching time T is more energy efficient than reducing the clock voltage swing V ϕ Voltage converter is inherently a pulse-to-level converter D in ϕ D CB ϕ D V ϕ 0 x l x l x p ϕ D x p ϕ D 150 ff T 150 ff V iso ϕ D D in 86 µm 07 µm V iso 07 µm D out 22 µm ϕ D 86 µm D out 22 µm

13 Energy vs Delay for all Drivers Clock buffer: set V ϕ (33-11 V) & T (0001 ns, 025 ns, 05 ns, 1 ns) Conventional drivers: set V ddl (33-11 V) Record energy for driving the load and delay through the converter Energy (pj) previous results Delay (ns) Inverter Modified Inv CB (0001ns) CB (025ns) CB (050ns) CB (100ns) Clock-powered approach has superior scalability because both clock voltage swing V ϕ and switching time T can be varied V ϕ 0 T

14 Clock-Powered Logic Design General approach: Use the clock rails to inject and recover the energy Derive as much operating power as possible from the clock rails General guidelines: Need an efficient clock driver Innovate in the design of a clock-steering logic Use conventional precharged, pass-transistor, static logic Use the clock-steering logic for high-capacitance loads clock driver clocksteering logic dc logic clocksteering logic dc logic clocksteering logic CMOS Chip dc logic Clock-Powered Nodes

15 Clock-Powered Logic for Optimized Energy vs Delay Reduce dissipation where dissipation is a problem Node-selective energy recovery Energy is recovered only from high-capacitance nodes clock-powered nodes: adiabatically switched 1 : pulsed to a clock-voltage swing V ϕ 0 : clamped at 0 V dc-powered nodes: conventionally switched 1 : pulled-up to a voltage V dd from a dc supply 0 : pulled-down to 0 V

16 The Energy Optimization Problem for Clock- Powered Logic Both clock-powered and dc-powered nodes contribute to energy dissipation The simplest expression that demonstrates the problem: E = E cp + E dc C cp» C dc for better energy efficiency Asymptotically E dc dominates RC cp C T cp V ϕ + 2 C dc V dd

17 Conclusions Clocked buffers offer better energy vs delay scalability than reducedvoltage drivers Energy depends on clock voltage swing and transition time Clock-powered logic is energy-efficient for implementing large-scale microsystems when: the system can be partitioned into C cp and C dc with effectively C cp» C dc long transition time of clock-powered nodes can be tolerated without changing overall system delay