EE434 ASIC & Digital Systems

Size: px
Start display at page:

Download "EE434 ASIC & Digital Systems"

Transcription

1 EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University Spring 2015 Dae Hyun Kim 1

2 Lecture 4 More on CMOS Gates Ref: Textbook chapter 2 Some of the slides are adopted from Digital Integrated Circuits by Jan M Rabaey 2

3 CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratio less Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors N fan-in gates need 2N transistors 3

4 Special CMOS Design Styles Ratioed Logic (Pseudo-nMOS) Dynamic CMOS Domino Logic Multiple-Output Domino Logic Dual-Rail Logic Pass Transistor Logic Transmissions Gate Logic 4

5 Ratioed Logic Pseudo NMOS Smaller area and load, but static power dissipation Follow board notes 5

6 Pseudo-nMOS More accurate computation PMOS: Saturation NMOS: Linear V DD 0 ββ nn 2 2 VV DDDD VV tttt VV OOOO VV OOOO 2 = ββ pp 2 (VV DDDD VV tttt ) 2 VV oooooo A VV OOOO = VV DDDD VV tttt VV DDDD VV tttt 2 ββ pp ββ nn (VV DDDD VV tttt ) 2 6

7 Pseudo-nMOS V DD V DD V DD 0 RR pp VV oooooo VV oooooo = VV DDDD RR nn VV oooooo = VV DDDD RR pp + RR nn A B C RR nn RR nn VV oooooo = 0.1VV DDDD = VV DDDD RR pp + RR nn RR pp = 9RR nn 7

8 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors 8

9 Dynamic CMOS Clk M p Clk M p Out Out In 1 In 2 In 3 Clk PDN (nfets) M n C L A B Clk M n C Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) 9

10 Dynamic CMOS Operation CCCC VV DDDD 0 Precharge Evaluate Precharge Evaluate tt Mp: ON Mp: OFF Mn: OFF Mn: ON 10

11 Dynamic CMOS FF = AA BB CC Mp VV oooooo A CC oooooo B C CK Mn 11

12 Dynamic CMOS Precharge Mp VV oooooo = 1 A CC oooooo B C CK=0 Mn 12

13 Dynamic CMOS Evaluation Mp VV oooooo = 0 oooo 1 A CC oooooo B C CK=1 Mn 13

14 Properties of Dynamic CMOS Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static CMOS gates) Full swing outputs Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (Cout) 14

15 Properties of Dynamic CMOS Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND no glitching higher transition probabilities extra load on Clk Needs a precharge/evaluate clock 15

16 Dynamic CMOS Charge sharing Mp VV oooooo A CC oooooo B CC 1 C CC 2 CK Mn CC 3 16

17 Dynamic CMOS Charge sharing Mp VV oooooo = VV DDDD VV oooooo A=0 VV 1 = 0 CC oooooo A=1 VV 11 CC oooooo B=0 VV 2 = 0 CC 1 B=1 VV 22 CC 1 C=0 CC 2 C=0 CC 2 CK=0 VV 3 = 0 CC 3 CK=1 Mn VV 3 = 0 CC 3 17

18 Dynamic CMOS Charge sharing VV oooooo = VV 1 = VV 2 QQ = CC oooooo VV DDDD = CC oooooo VV ff + CC 1 VV ff + CC 2 VV ff = CC oooooo + CC 1 + CC 2 VV ff VV ff = ( CC oooooo CC oooooo +CC 1 +CC 2 )VV DDDD A=1 VV 11 VV oooooo CC oooooo B=1 VV 22 CC 1 C=0 CC 2 Mn VV 3 = 0 CC 3 18

19 Dynamic CMOS How to solve the charge sharing problem Constraint: CC oooooo CC 1 + CC 2 Keeper Keeper Clk M p M kp A B C L Out Clk M e 19

20 Dynamic CMOS How to solve the charge sharing problem Clk A M p M kp Out Clk B Clk M e Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) 20

21 Domino Logic CK 21

22 Domino Logic PDN PDN PDN CK 22

23 Domino Logic Example SSSSSS = aa bb cc a b c Sum XX XX SSSSSS a aa a aa X XX b bb bb b cc c CK CK CK 23

24 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced 24

25 Multiple-Output Domino Logic (MODL) ff 1 = GG ff 2 = FF GG ff 2 = FF GG F ff 1 = GG G CK 25

26 Dual-Rail Logic Network Differential Cascode Voltage Switch Logic (DCVSL) VV DDDD ff ff XX 1 XX 2 XX 3 Logic tree XX 1 XX 2 XX 3 26

27 Dual-Rail Logic Network Differential Cascode Voltage Switch Logic (DCVSL) VV DDDD VV DDDD ff ff aa bb aa bb XX 1 XX 2 Logic tree XX 1 XX 2 aa bb aa XX 3 XX 3 bb 27

28 Pass Transistor Logic B Inputs Switch Network Out A B B Out N transistors No static consumption 28

29 Pass Transistor Logic Example BB BB AA AA BB FF = AA BB BB FF = AA + BB

30 Issues with Pass Transistor Logic Threshold drop Capacitive feed through Charge sharing Follow board notes VV DDDD VV tttt VV DDDD 2VV tttt 30

31 Pass Transistor Logic Capacitive Feedthrough VV DDDD 0VV G CC ff VV oooooo VV iiii D S CC gggggg 0VV 31

32 Transmission Gate Logic A S S VDD M2 F The control signal S turns the transfer gates on and off depending on its value. When s=1, the upper transfer gate is on and that allows A to follow to the output M1 B S Implement the Multiplexer with static CMOS and compare with this 32

33 Transmission Gate Logic B M2 B A M1 B F B A M3/M4 33

Physical Structure of CMOS Integrated Circuits

Physical Structure of CMOS Integrated Circuits Physical Structure of CMOS Integrated Circuits Dae Hyun Kim EECS Washington State University References John P. Uyemura, Introduction to VLSI Circuits and Systems, 2002. Chapter 3 Neil H. Weste and David

More information

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Objectives In this lecture you will learn the following Ratioed Logic Pass Transistor Logic Dynamic Logic Circuits

More information

EEC 118 Lecture #12: Dynamic Logic

EEC 118 Lecture #12: Dynamic Logic EEC 118 Lecture #12: Dynamic Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Today: Alternative MOS Logic Styles Dynamic MOS Logic Circuits: Rabaey

More information

Combinational Logic Gates in CMOS

Combinational Logic Gates in CMOS Combinational Logic Gates in CMOS References: dapted from: Digital Integrated Circuits: Design Perspective, J. Rabaey UC Principles of CMOS VLSI Design: Systems Perspective, 2nd Ed., N. H. E. Weste and

More information

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals

More information

Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,

More information

Dynamic Logic. Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic 11/28/2012 1

Dynamic Logic. Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic 11/28/2012 1 Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT 2 will be reviewed. We will review the following logic families: Domino logic P-E logic

More information

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought

More information

EE241 - Spring 2002 Advanced Digital Integrated Circuits

EE241 - Spring 2002 Advanced Digital Integrated Circuits EE241 - Spring 2002 dvanced Digital Integrated Circuits Lecture 7 MOS Logic Styles nnouncements Homework #1 due 2/19 1 Reading Chapter 7 in the text by K. ernstein ackground material from Rabaey References»

More information

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation

More information

VLSI Logic Structures

VLSI Logic Structures VLSI Logic Structures Ratioed Logic Pass-Transistor Logic Dynamic CMOS Domino Logic Zipper CMOS Spring 25 John. Chandy inary Multiplication + x Multiplicand Multiplier Partial products Result Spring 25

More information

Power-Area trade-off for Different CMOS Design Technologies

Power-Area trade-off for Different CMOS Design Technologies Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head

More information

UNIT-III GATE LEVEL DESIGN

UNIT-III GATE LEVEL DESIGN UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms

More information

1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)

1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,

More information

EE 330 Lecture 42. Other Logic Styles Digital Building Blocks

EE 330 Lecture 42. Other Logic Styles Digital Building Blocks EE 330 Lecture 42 Other Logic Styles Digital Building Blocks Logic Styles Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic Domino Zipper Static CMOS Widely used Attractive

More information

EE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 7. Clocked and self-resetting logic I

EE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 7. Clocked and self-resetting logic I EE E6930 Advanced Digital Integrated Circuits Spring, 2002 Lecture 7. Clocked and self-resetting logic I References CBF, Chapter 8 DP, Section 4.3.3.1-4.3.3.4 Bernstein, High-speed CMOS design styles,

More information

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R R 6 W 1 C C 3 D R t 1 R R t 2 R R t

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit

More information

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R RW 6 W 1 C C 3 D R t 1 R R t 2 R R t

More information

ECE 471/571 Combinatorial Circuits Lecture-7. Gurjeet Singh

ECE 471/571 Combinatorial Circuits Lecture-7. Gurjeet Singh ECE 471/571 Combinatorial Circuits Lecture-7 Gurjeet Singh Propagation Delay of CMOS Gates Propagation delay of Four input NAND Gate Disadvantages of Complementary CMOS Design Increase in complexity Larger

More information

IJMIE Volume 2, Issue 3 ISSN:

IJMIE Volume 2, Issue 3 ISSN: IJMIE Volume 2, Issue 3 ISSN: 2249-0558 VLSI DESIGN OF LOW POWER HIGH SPEED DOMINO LOGIC Ms. Rakhi R. Agrawal* Dr. S. A. Ladhake** Abstract: Simple to implement, low cost designs in CMOS Domino logic are

More information

Lecture 13 CMOS Power Dissipation

Lecture 13 CMOS Power Dissipation EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 13 CMOS Power Dissipation Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken,

More information

2-Bit Magnitude Comparator Design Using Different Logic Styles

2-Bit Magnitude Comparator Design Using Different Logic Styles International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 2 Issue 1 ǁ January. 2013 ǁ PP.13-24 2-Bit Magnitude Comparator Design Using Different Logic

More information

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit

More information

Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles

Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles Mangayarkkarasi M 1, Joseph Gladwin S 2 1 Assistant Professor, 2 Associate Professor 12 Department of ECE 1 Sri

More information

EE 330 Lecture 44. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 44. Digital Circuits. Other Logic Styles Dynamic Logic Circuits EE 330 Lecture 44 Digital Circuits Other Logic Styles Dynamic Logic Circuits Course Evaluation Reminder - ll Electronic http://bit.ly/isustudentevals Review from Last Time Power Dissipation in Logic Circuits

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Ratioed Logic Introduction Digital IC EE141 2 Ratioed Logic design Basic concept Resistive load Depletion

More information

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

More information

EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families

EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Homework 5 this week Lab

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa atarina enter for Technology omputer Science & Electronics Engineering Integrated ircuits & Systems INE 5442 Lecture 16 MOS ombinational ircuits - 2 guntzel@inf.ufsc.br Pass

More information

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI

More information

Domino Static Gates Final Design Report

Domino Static Gates Final Design Report Domino Static Gates Final Design Report Krishna Santhanam bstract Static circuit gates are the standard circuit devices used to build the major parts of digital circuits. Dynamic gates, such as domino

More information

Homework Assignment 09

Homework Assignment 09 Question 1 (2 points each unless noted otherwise) Homework Assignment 09 1. For SPICE, Explain very briefly the difference between the multiplier M and Meg, as in a resistor has value 2M versus a resistor

More information

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute.  From state elements ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

More information

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey

More information

ECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh

ECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh NMOS-to-PMOS ratio,pmos are made β times larger than NMOS Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing

More information

Chapter 2 Combinational Circuits

Chapter 2 Combinational Circuits Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits

More information

IMPLEMENTATION OF LOW POWER AND LOW ENERGY SYNCHRONOUS SAPT LOGIC

IMPLEMENTATION OF LOW POWER AND LOW ENERGY SYNCHRONOUS SAPT LOGIC IMPLEMENTATION OF LOW POWER AND LOW ENERGY SYNCHRONOUS SAPT LOGIC Chitambara Rao.K 1,Nagendra.K 2 Sreenivasa Rao.Ijjada 3 1 Department of ECE, AITAM College of Engineering, Tekkali, Srikakulam,India rao_chidu@ymail.com

More information

VLSI Design. Static CMOS Logic

VLSI Design. Static CMOS Logic VLSI esign Static MOS Logic [dapted from Rabaey s igital Integrated ircuits, 2002, J. Rabaey et al.] EE4121 Static MOS Logic.1 ZLM Review: MOS Process at a Glance efine active areas Etch and fill trenches

More information

Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles

Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-237, Volume-2, Issue-6, Jan- 213 Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles

More information

! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.

! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology.  Gate choice, logical optimization.  Fanin, fanout, Serial vs. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!

More information

MOS Logic and Gate Circuits. Wired OR

MOS Logic and Gate Circuits. Wired OR MOS Logic and Gate Circuits A A A B A AB Y Wired OR Contents Introduction NMOS Logic Resistive Load Saturated Enhancement Load Linear Enhancement Load Depletion Load Some Gates Transient in NMOS Circuit

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

Announcements. Advanced Digital Integrated Circuits. Quiz #3 today Homework #4 posted This lecture until 4pm

Announcements. Advanced Digital Integrated Circuits. Quiz #3 today Homework #4 posted This lecture until 4pm EE241 - Spring 2011 dvanced Digital Integrated Circuits Lecture 20: High-Performance Logic Styles nnouncements Quiz #3 today Homework #4 posted This lecture until 4pm Reading: Chapter 8 in the owhill text

More information

! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.

! Review: Sequential MOS Logic.  SR Latch.  D-Latch. ! Timing Hazards. ! Dynamic Logic.  Domino Logic. ! Charge Sharing Setup. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "

More information

EE434 ASIC & Digital Systems. Partha Pande School of EECS Washington State University

EE434 ASIC & Digital Systems. Partha Pande School of EECS Washington State University EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 11 Physical Design Issues Interconnect Scaling Effects Dense multilayer metal increases coupling

More information

Design of Low Power Vlsi Circuits Using Cascode Logic Style

Design of Low Power Vlsi Circuits Using Cascode Logic Style Design of Low Power Vlsi Circuits Using Cascode Logic Style Revathi Loganathan 1, Deepika.P 2, Department of EST, 1 -Velalar College of Enginering & Technology, 2- Nandha Engineering College,Erode,Tamilnadu,India

More information

ELEC Digital Logic Circuits Fall 2015 Delay and Power

ELEC Digital Logic Circuits Fall 2015 Delay and Power ELEC - Digital Logic Circuits Fall 5 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal

More information

COMPREHENSIVE ANALYSIS OF ENHANCED CARRY-LOOK AHEAD ADDER USING DIFFERENT LOGIC STYLES

COMPREHENSIVE ANALYSIS OF ENHANCED CARRY-LOOK AHEAD ADDER USING DIFFERENT LOGIC STYLES COMPREHENSIVE ANALYSIS OF ENHANCED CARRY-LOOK AHEAD ADDER USING DIFFERENT LOGIC STYLES PSowmya #1, Pia Sarah George #2, Samyuktha T #3, Nikita Grover #4, Mrs Manurathi *1 # BTech,Electronics and Communication,Karunya

More information

Timing and Power Optimization Using Mixed- Dynamic-Static CMOS

Timing and Power Optimization Using Mixed- Dynamic-Static CMOS Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2013 Timing and Power Optimization Using Mixed- Dynamic-Static CMOS Hao Xue Wright State University Follow

More information

Investigating Delay-Power Tradeoff in Kogge-Stone Adder in Standby Mode and Active Mode

Investigating Delay-Power Tradeoff in Kogge-Stone Adder in Standby Mode and Active Mode Investigating Delay-Power Tradeoff in Kogge-Stone Adder in Standby Mode and Active Mode Design Review 2, VLSI Design ECE6332 Sadredini Luonan wang November 11, 2014 1. Research In this design review, we

More information

CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS

CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS 70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 11 BiCMOS PMOS rray Q1 NMOS rray Y NMOS rray Q2 dib brishamifar EE Department IUST Contents Introduction BiCMOS Devices BiCMOS Inverters BiCMOS Gates BiCMOS Drivers

More information

Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages

Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages RESEARCH ARTICLE OPEN ACCESS Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages A. Suvir Vikram *, Mrs. K. Srilakshmi ** And Mrs. Y. Syamala *** * M.Tech,

More information

Written Examination on. Wednesday October 17, 2007,

Written Examination on. Wednesday October 17, 2007, Written Examination on Wednesday October 17, 2007, 08.00-12.00 The textbook and a calculator are allowed on the examination 1. The following logical function is given Q= AB( CD+ CE) + F a. Draw the schematic

More information

CMOS Circuits CONCORDIA VLSI DESIGN LAB

CMOS Circuits CONCORDIA VLSI DESIGN LAB CMOS Circuits 1 Combination and Sequential 2 Static Combinational Network CMOS Circuits Pull-up network-pmos Pull-down network-nmos Networks are complementary to each other When the circuit is dormant,

More information

Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology

Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology 1 Mahesha NB #1 #1 Lecturer Department of Electronics & Communication Engineering, Rai Technology University nbmahesh512@gmail.com

More information

Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits

Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits Research Journal of Applied Sciences, Engineering and Technology 5(10): 2991-2996, 2013 ISSN: 2040-7459; e-issn: 2040-7467 Maxwell Scientific Organization, 2013 Submitted: September 16, 2012 Accepted:

More information

Lecture 10. Circuit Pitfalls

Lecture 10. Circuit Pitfalls Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski

More information

ISSN: [Kumar* et al., 6(5): May, 2017] Impact Factor: 4.116

ISSN: [Kumar* et al., 6(5): May, 2017] Impact Factor: 4.116 IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY IMPROVEMENT IN NOISE AND DELAY IN DOMINO CMOS LOGIC CIRCUIT Ankit Kumar*, Dr. A.K. Gautam * Student, M.Tech. (ECE), S.D. College

More information

EECS 141: FALL 98 FINAL

EECS 141: FALL 98 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you

More information

High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers

High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency

More information

Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications

Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications LETTER IEICE Electronics Express, Vol.12, No.3, 1 6 Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications Xin-Xiang Lian 1, I-Chyn Wey 2a), Chien-Chang Peng 3, and

More information

International Journal of Advanced Research in Biology Engineering Science and Technology (IJARBEST)

International Journal of Advanced Research in Biology Engineering Science and Technology (IJARBEST) Abstract NEW HIGH PERFORMANCE 4 BIT PARALLEL ADDER USING DOMINO LOGIC Department Of Electronics and Communication Engineering UG Scholar, SNS College of Engineering Bhuvaneswari.N [1], Hemalatha.V [2],

More information

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.

More information

BICMOS Technology and Fabrication

BICMOS Technology and Fabrication 12-1 BICMOS Technology and Fabrication 12-2 Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with

More information

Low-Power Digital CMOS Design: A Survey

Low-Power Digital CMOS Design: A Survey Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with

More information

EECS 427 Lecture 22: Low and Multiple-Vdd Design

EECS 427 Lecture 22: Low and Multiple-Vdd Design EECS 427 Lecture 22: Low and Multiple-Vdd Design Reading: 11.7.1 EECS 427 W07 Lecture 22 1 Last Time Low power ALUs Glitch power Clock gating Bus recoding The low power design space Dynamic vs static EECS

More information

DESIGN AND IMPLEMENTATION OF NOVEL HIGH PERFORMANCE DOMINO LOGIC. Doctor of Philosophy. VLSI Design and Embedded Systems

DESIGN AND IMPLEMENTATION OF NOVEL HIGH PERFORMANCE DOMINO LOGIC. Doctor of Philosophy. VLSI Design and Embedded Systems DESIGN AND IMPLEMENTATION OF NOVEL HIGH PERFORMANCE DOMINO LOGIC A thesis submitted in partial fulfillment of the requirements for the award of the degree of Doctor of Philosophy in VLSI Design and Embedded

More information

Unit WorkBook 1 Level 4 ENG U22 Electronic Circuits and Devices 2018 UniCourse Ltd. All Rights Reserved. Sample

Unit WorkBook 1 Level 4 ENG U22 Electronic Circuits and Devices 2018 UniCourse Ltd. All Rights Reserved. Sample Pearson BTEC Level 4 Higher Nationals in Engineering (RQF) Unit 22: Electronic Circuits and Devices Unit Workbook 1 in a series of 4 for this unit Learning Outcome 1 Operational Amplifiers Page 1 of 23

More information

COMPARATIVE ANALYSIS OF 32 BIT CARRY LOOK AHEAD ADDER USING HIGH SPEED CONSTANT DELAY LOGIC

COMPARATIVE ANALYSIS OF 32 BIT CARRY LOOK AHEAD ADDER USING HIGH SPEED CONSTANT DELAY LOGIC COMPARATIVE ANALYSIS OF 32 BIT CARRY LOOK AHEAD ADDER USING HIGH SPEED CONSTANT DELAY LOGIC V.Reethika Rao (1), Dr.K.Ragini (2) PG Scholar, Dept of ECE, G. Narayanamma Institute of Technology and Science,

More information

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 9 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline CMOS (n-channel based MOSFETs based circuit) CMOS Features

More information

Chapter 4. Problems. 1 Chapter 4 Problem Set

Chapter 4. Problems. 1 Chapter 4 Problem Set 1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock network (between the nodes) is 5 mm long, 3 µm wide, and is implemented

More information

Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits

Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits by Shahrzad Naraghi A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

International Journal of Scientific & Engineering Research, Volume 6, Issue 7, July ISSN

International Journal of Scientific & Engineering Research, Volume 6, Issue 7, July ISSN International Journal of Scientific & Engineering Research, Volume 6, Issue 7, July-2015 636 Low Power Consumption exemplified using XOR Gate via different logic styles Harshita Mittal, Shubham Budhiraja

More information

Analysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision

Analysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision Analysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision Ashish Panchal (Senior Lecturer) Electronics & Instrumentation Engg. Department, Shri G.S.Institute of Technology

More information

Double Stage Domino Technique: Low- Power High-Speed Noise-tolerant Domino Circuit for Wide Fan-In Gates

Double Stage Domino Technique: Low- Power High-Speed Noise-tolerant Domino Circuit for Wide Fan-In Gates Double Stage Domino Technique: Low- Power High-Speed Noise-tolerant Domino Circuit for Wide Fan-In Gates R Ravikumar Department of Micro and Nano Electronics, VIT University, Vellore, India ravi10ee052@hotmail.com

More information

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #08 Spring, 2001 (Due 04/26/2001) Choma Problem #35: The NMOS transistors in the

More information

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology Kyung Ki Kim a) and Yong-Bin Kim b) Department of Electrical and Computer Engineering, Northeastern University, Boston, MA

More information

Adiabatic Logic. Benjamin Gojman. August 8, 2004

Adiabatic Logic. Benjamin Gojman. August 8, 2004 Adiabatic Logic Benjamin Gojman August 8, 2004 1 Adiabatic Logic Adiabatic Logic is the term given to low-power electronic circuits that implement reversible logic. The term comes from the fact that an

More information

UNIT-II LOW POWER VLSI DESIGN APPROACHES

UNIT-II LOW POWER VLSI DESIGN APPROACHES UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.

More information

ECE380 Digital Logic. Logic values as voltage levels

ECE380 Digital Logic. Logic values as voltage levels ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the

More information

Electronics Basic CMOS digital circuits

Electronics Basic CMOS digital circuits Electronics Basic CMOS digital circuits Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED October 21, 2014 1 / 30 Introduction The topics covered today: The inverter: the simplest

More information

EE241 - Spring 2006 Advanced Digital Integrated Circuits. Notes. Lecture 7: Logic Families for Performance

EE241 - Spring 2006 Advanced Digital Integrated Circuits. Notes. Lecture 7: Logic Families for Performance EE241 - Spring 2006 dvanced Digital Integrated Circuits Lecture 7: Logic Families for Performance Notes Hw 1 due tomorrow Feedback on projects will be sent out by the end of the weekend Some thoughts on

More information

Design of 32-bit ALU using Low Power Energy Efficient Full Adder Circuits

Design of 32-bit ALU using Low Power Energy Efficient Full Adder Circuits Design of 32-bit ALU using Low Power Energy Efficient Full Adder Circuits Priyadarshini.V Department of ECE Gudlavalleru Engieering College,Gudlavalleru darshiniv708@gmail.com Ramya.P Department of ECE

More information

Domino CMOS Implementation of Power Optimized and High Performance CLA adder

Domino CMOS Implementation of Power Optimized and High Performance CLA adder Domino CMOS Implementation of Power Optimized and High Performance CLA adder Kistipati Karthik Reddy 1, Jeeru Dinesh Reddy 2 1 PG Student, BMS College of Engineering, Bull temple Road, Bengaluru, India

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f

More information

A Low-Power High-speed Pipelined Accumulator Design Using CMOS Logic for DSP Applications

A Low-Power High-speed Pipelined Accumulator Design Using CMOS Logic for DSP Applications International Journal of Research Studies in Computer Science and Engineering (IJRSCSE) Volume. 1, Issue 5, September 2014, PP 30-42 ISSN 2349-4840 (Print) & ISSN 2349-4859 (Online) www.arcjournals.org

More information

55:141 Advanced Circuit Techniques Switching Regulators

55:141 Advanced Circuit Techniques Switching Regulators 55:141 Advanced Circuit Techniques Switching Regulators Material: ecture Notes, Handouts, and Sections of Chapter 11 of Franco A. Kruger 55:141: Advanced Circuit Techniques The University of Iowa Switching

More information

ECE520 VLSI Design. Lecture 11: Combinational Static Logic. Prof. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 11: Combinational Static Logic. Prof. Payman Zarkesh-Ha EE520 VLSI esign Lecture 11: ombinational Static Logic Prof. Payman Zarkesh-Ha Office: EE ldg. 230 Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 eview of Last

More information

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 77-81 International Research Publication House http://www.irphouse.com Noise Tolerance Dynamic CMOS Logic

More information

Digital Microelectronic Circuits ( ) Pass Transistor Logic. Lecture 9: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) Pass Transistor Logic. Lecture 9: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 9: Pass Transistor Logic 1 Motivation In the previous lectures, we learned about Standard CMOS Digital Logic design. CMOS

More information

Power Efficient and Noise Immune Domino Logic for Wide Fan in Gates

Power Efficient and Noise Immune Domino Logic for Wide Fan in Gates Power Efficient and Noise Immune Domino Logic for Wide Fan in Gates K.Venkata laxmi¹, B.Lakshmi² PG Student [VLSI], Dept. of ECE, GVP College of Engineering, Visakhapatnam, Andhra Pradesh, India 1 Assistant

More information

Design of Multipliers Using Low Power High Speed Logic in CMOS Technologies

Design of Multipliers Using Low Power High Speed Logic in CMOS Technologies Design of Multipliers Using Low Power High Speed Logic in CMOS Technologies Linet. K 1, Umarani.P 2, T. Ravi 3 M.Tech VLSI Design, Dept. of ECE, Sathyabama University, Chennai, Tamilnadu, India 1 Assistant

More information

Investigation on Performance of high speed CMOS Full adder Circuits

Investigation on Performance of high speed CMOS Full adder Circuits ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Investigation on Performance of high speed CMOS Full adder Circuits 1 KATTUPALLI

More information

Implementation of High Performance Carry Save Adder Using Domino Logic

Implementation of High Performance Carry Save Adder Using Domino Logic Page 136 Implementation of High Performance Carry Save Adder Using Domino Logic T.Jayasimha 1, Daka Lakshmi 2, M.Gokula Lakshmi 3, S.Kiruthiga 4 and K.Kaviya 5 1 Assistant Professor, Department of ECE,

More information

Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B

Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied

More information

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative

More information