Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:

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1 Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, And following the midterm, we will cover PN diodes again in forward bias, and develop small signal models: Chapter 6 we will then take a week on bipolar junction transistor (BJT): Chapter 7 Then go on to design of transistor amplifiers: chapter 8 Context Digital techniques: In the last few lectures, we discussed the MOS transistor, built some models for how it operates. This is an analog course, but in this lecture, we will take a brief look at how MOS transistors are used for digital circuits: most analog circuits need to interface with digital devices Analog functions are important for many digital devices The most important concept in digital processing is the transfer of information by discrete states (for example, or s). At each stage, any value close to can be taken to be the same as exactly, and any voltage close to 1 volt has the same meaning as 1 volt. Because of this limitation, each stage can keep the information passed to the next stage pure, rather than have it degraded slightly by each one. (by imperfections or noise) 1

2 Real switch logic Digital logic levels An example of logic still using real switches is the circuit used to turn a light on from two different places, for example at the ends of a hallway A switch being closed by an input voltage can pull the output to a voltage. Since the gain of a transistor can be high, the output can be closer to the ideal level ~ Logic true, 1 Input output The light only goes on when both switches are up, or if they are both down. Logic false, 0 Input output Boole and Turing AND In 1985 George Boole, a mathematician, worked out that a complete set of logical processes can be derived from the elemental processes of AND, OR, and Inversion, thought to be pretty useless at the time! To make an AND gate, we can use two switches Input A Input B Later Alan Turing worked out that a general computing machine can be made from a sequence of these simple operations.

3 OR Logic Families To make an OR gate, we can use two switches Input A Input B Mechanical relays were used for logic functions over 100 years ago. For example, telephone systems and elevators used relay logic into the 1960 s. Vacuum electron tubes were used in the 1940 s and 1950 s. They produced a lot of heat and were unreliable. The first logic families were made using BJT s, using the diffusion of minority carriers. Until recently, BJT based logic was the fastest semiconductor logic and then were used in the 1970 s and 1980 s CMOS, the combination of and, became dominant over the last decade, because of lower power dissipation. Inverter Simplified large signal model To make an inverter, we can use one switch A FET as a resistive switch: G + D + Input As long as the switch is closed, even just barely, the output is. If the switch is open, the output Is 1 volt V GS The switch is closed if the gate is higher than the source by the amount of the threshold C S R V DS 3

4 Circuit Symbols Load line N channel MOS FET P channel MOS FET I DS / k µa = 4V = 3V I DS 1 MΩ 3 volts V GS Digital Both and transistors can look like switches switches are on when the gate is at a higher positive voltage switches are on when the gate is at a lower voltage The body of a transistor is usually at ground() The body of a transistor is usually put at V CC = V Since the current through the resistor is equal to the drain current, and the sum of the voltages must add up to,, we can draw a straight line on the plot of VDS vs IDS which has the allowed voltages and currents (since V = ) This is called a load line. The slope of the load line R I RR is the resistance of the pull up resistor( 1 MΩ here), and the intercept of 0 current occurs when the full voltage drop occurs across the resistor (3 volts) V DS inverter Logic levels We can make an inverter by using a resistor as a pull up device I DS / k µa = 4V I DS 1 MΩ 3 volts = 3V V GS Input = V V DS If the gate has around three volts on it, then the voltage at the output will be determined by the purple (upper) circle, and if the gate is bias to around zero volts, the output voltage will be determined by the red (lower) circle. Notice that the output voltage in the high state is only about 1. volts, So the next transistor may not be biased below threshold. 4

5 Logic levels Gain I DS / k µa = 4V = 3V I DS 3 MΩ 3 volts For our resistor pullup inverter, however, the plot of output voltage vs. input voltage looks something like this: V GS = V If the resistance of the pull up resistor is increased to 3 MΩ, then the output voltage in the low state will be about.5 volts, which should put the next transistor below threshold. However, the current in the case that the input is true is still 1 microamp, which is a large amount of current for one gate to use, and integrated MΩ resistors are difficult to make V DS Gain Noise margin If output voltage of an inverter is plotted vs. the input voltage, what you want to see is that the output is made closer to a good logic level than the input was. For a perfect inverter, you would have a curve like this: Voltage The fact that the logic high does not come all the way up to Vdd means that the circuit has a reduced resistance to noise. The voltage where Vin=Vout is also about 1.75 volts, rather than half way in between the logic low and logic high levels, further decreasing the resistance to noise Input voltage 5

6 Inverter DC Analysis OR R 1 R In DC analysis, we are essentially computing the competing devices to pull up the output to Vdd, and those pulling the output to ground Ideally, we would like the ratio of resistances to be high, so that we get output voltages near the rails. A good way of doing this is to use two switches, and to open one while the other is closed This would allow us to pull the voltage all the way to ground or Vdd, and would eliminate DC currents We can also make AND gates and OR gates with switches for both pull up and pull down Input B Input A NOT Input A NOT Input B Inverter DC Analysis AND R 1 R Of course, neither of the switches can be perfectly open, or have zero resistance when closed, but MOS transistors can come pretty close. In addition, MOS transistors have their gate insulated by the gate oxide from the source and drain, so they don t use any DC power into their input, either. Of course, there is still power dissipation when the switches are closed Input A Input B NOT Input A NOT Input B 6

7 Transient Response CMOS inverter R p Whenever there is a change at the inputs, the change in the output voltage will require driving current through the switches that are still on, charging the load capacitance When Vin is near Vdd, the transistor will conduct, and the transistor will be in cutoff C L C L R n C L The time that it takes to charge the capacitance is just the RC time constant of the capacitance together with the ON resistance of the switches. For fast logic, we want low capacitance and low resistance. Since the current through the gate scales with W, we could make that large, but that will also make C large (from the next stage) CMOS inverter CMOS Inverter If a and transistor are hooked up like this, if Vin is near the transistor will be cut off, and the transistor will be well above threshold and conducting In Out N Well λ Contacts Polysilicon In Out Metal 1 ~ in C L GND 7

8 CMOS Inverter Load Characteristics = 1.5 = =.5 I Dn = 0 = 0.5 = 1 = 1.5 = 1.5 = 1 =.5 = = 1 = 0.5 = 0 In steady state, the drain current from the device must go through the device, so each forms a load line for the other. Because of the high resistance in the off state, the logic levels come very close to and Vdd. CMOS Since the pairing of and transistors can pull the logic levels all the way to 0 for the low state and Vdd for the high state, it greatly improves noise resistance. Since one of the sets of transistors is always off, and the inputs to both and devices are capacitive only, there is no static dissipation. Dynamic dissipation comes from charging of the capacitive inputs. CMOS Dynamic dissipation The plot of the output voltage vs the input voltage would look something like this: Vout Vin In a CMOS logic gate, the current from the power supply goes almost entirely to charging the capacitance of the next stage. The power it takes is: P = VI The current is supplied at a voltage, To find the energy per transition, we integrate over the switching time. Energy = P( t) dt = VDD I( t) dt = VDDQ = CV So it helps both to reduce operating voltages, and capacitances DD 8

9 Level shifting In many new VLSI devices, internal voltages are kept low for lower dissipation, but they still need to work with other chips at higher voltages. Therefore, level shifters need to be provided at the inputs and outputs. High level outputs are essentially amplifiers, which we will be studying soon. Multiple stages may be needed for high currents. High level inputs: voltages above the body voltage of the transistors must be avoided, otherwise the source to body junction will be forward biased, with high currents 9