Field Effect Transistors

Transcription

1 Field Effect Transistors Purpose In this experiment we introduce field effect transistors (FETs). We will measure the output characteristics of a FET, and then construct a common-source amplifier stage, analogous to the common-emitter bipolar amplifier we studied in Experiment 7. Introduction As we discussed in Experiment 7, transistors are the basic devices used to amplify electrical signals. They come in two general types, bipolar junction transistors (BJTs) and field effect transistors (FETs). The input to a FET is called the gate. (Remember from Experiment 7: the input to a BJT is called the base.) But unlike the situation with bipolar transistors, almost no current flows into the gate. FETs are voltage controlled current amplifiers with very high input impedance. (Remember from Experiment 7: BJTs are current controlled current amplifiers.) In junction FETs (JFETs) the gate is connected to the rest of the device through a reverse biased pn junction, while in metaloxide-semiconductor FETs (MOSFETs) the gate is connected via a thin insulating oxide layer. JFETs have much lower noise than MOSFETs but are more difficult to manufacture in integrated circuits. Bipolar transistors come in two polarities called npn and pnp, and similarly FETs come in two polarities called n-channel and p-channel. In integrated circuit form, small MOSFETs are ubiquitous in digital electronics, used in everything from simple logic circuits to the currently (2012) ~4 billion transistor Altera Stratix-V FPGA chip or the ~16+ billion transistors 2GB memory chips. Small MOSFETs are also used in some opamps, particularly when very low supply current is needed, such as in portable battery-powered circuits. Small discrete (single) MOSFETs are not normally used because they are extremely fragile. Large discrete MOSFETs are used in all sorts of high power applications, including commercial radio transmitters or audio amplifiers. JFETs generate very little noise themselves, thus a JFET input op-amp is often the first choice for low-noise amplification. Discrete JFETs are commonly seen in scientific instruments. In this experiment we will study an n-channel JFET (the 2N4416A) with excellent low-noise performance. Like bipolar transistors, JFETs suffer from wide process spread, meaning that critical parameters vary greatly from part to part. We will start by measuring the properties of a single device so that we can predict how it will behave in a circuit. Then we will build a common-source amplifier from our characterized JFET, and check its quiescent operating voltages and gain. 8.1

2 Readings 1. FC Chapter 8 (Field effect transistor) 2. Amplifier and resistor noise is discussed in H&H sections Sections of H&H introduce FETs and analog FET circuits. You might find that this is more than you want or need to know about FETs. 4. Application Note AN101 An Introduction to JFETs from Vishay/Siliconix. There is a link to it on our course web site. You will also find on our web site the data sheet for the 2N4416A, the n-channel JFET we will be using. 5. If you are on campus you can read the original 1934 papers on resistor thermal noise by Johnson and Nyquist. See the links on our web site. 8.2

3 Theory V DS I D D D G S 0 V to -5 V G S (a) (b) Figure 8.1 a) N-channel JFET b) Measuring Output Characteristics. Note that the gate voltage is negative. JFET CHARACTERISTICS The schematic symbol shown in Fig. 8.1a is used for the n-channel JFET. For the p-channel version the arrow points the other way and all polarities discussed below would be reversed. The three leads are gate (G), drain (D), and source (S). The path from drain to source through which the output current normally flows is called the channel. In many ways, the gate, drain and source are analogous to the base, collector and emitter of an npn transistor. However, in normal operation the gate voltage is below the source voltage (this keeps the gate pn junction reverse biased) and almost no current flows out of the gate. The voltage of the gate relative to the source (V GS ) controls how much current flows from drain to source through the channel. For more detail, look at the Output Characteristics graphs on page 7.3 of the 2N4416A data sheet. The drain-to-source current (I D ) is plotted versus the drain-to-source voltage (V DS ) for various values of the controlling gate-source voltage (V GS ). The JFET is normally operated with V DS greater than about 3 V, in the saturation region where the curves have only a small slope as a function of V GS. In this region the current is nearly constant (i.e. nearly independent of V DS ), but controlled by V GS. Thus the JFET can be viewed as a voltage-controlled current source. The gain of a JFET is described by the transconductance gfs: g fs δi δv D GS 8.3

4 which tells us how much change in drain current results from a small change in the gate voltage. Hence the transconductance is the slope of the I D vs. V GS ) curve, but this curve is often not plotted in the specifications and you may have to generate it yourself. This quantity is called a conductance because it has the dimensions of inverse Ohms, and a transconductance because the current and voltage are not at the same terminal. In the SI system 1/Ω is called a Siemens (S). According to the data sheet, gfs is guaranteed to be between 4.5 and 7.5 ms at V GS = 0 for V DS = 15V. Since a Siemens is an ampere per volt, this means that the drain current I D changes by 4.5 to 7.5 ma when the gate voltage V GS changes by 1 volt. Like the β or h FE of a bipolar transistor, gfs is not really a constant, and it has large process variations. The transconductance only varies a little with V DS as long as V DS is greater than about 3V. The dependence on V GS is more rapid (see the plot on the data sheet). The transconductance is maximum at V GS = 0. V GS 0 is where the best noise performance occurs, so you will build your amplifier for this condition. Other properties of the JFET also have large process variations. The saturation drain current I DSS is the value of I D at V GS = 0 and some large value of V DS, usually 15 V. You can see that this quantity is about 7 and 11 ma for the two devices in the plots at the bottom of page 7.3 of the data sheet. According to the table on page 7-2, I DSS is guaranteed to be between 5 and 15 ma, a very wide range for the designer to cope with. Another useful quantity is the gate-source cutoff voltage V GS(off), the value of V GS where I D drops to zero. For the two devices on page 7.3 this is -2 V and -3 V, but the data sheet only promises that it will be between -2.5V and -6V, again a very wide range. Because of the wide variation of JFET parameters, a good starting point for any JFET circuit development is to plot your own output characteristic curves for the device at hand. There is an instrument called a curve tracer that can do this for you automatically, but in this lab we will let you do it once by hand, using the set-up shown in Fig. 8.1b on p The drain is connected to a variable voltage source that controls V DS, and there is a current meter (ideally with zero voltage drop across it) in series with the drain to measure I D. You also need a (negative) variable voltage source between the gate and ground to set V GS. Finally, a voltmeter between the gate and ground is used to measure V GS. COMMON SOURCE AMPLIFIER A JFET common-source amplifier stage is shown in Fig (Notice the similarities to a commonemitter amplifier based on a BJT.) To keep things simple we are supposing that the input signal has a dc value of 0 V, so the desired quiescent gate voltage (V GS =0) is achieved without the need for a dc blocking capacitor and a voltage divider like we used for our bipolar common-emitter amplifier. 8.4

5 A small change in the input voltage δv in ( = δv GS in this circuit) causes a change in the drain current equal to gfs V in, and this current dropped across the drain resistor R D causes an output voltage δv out = -R D gfs δv in. Thus, the voltage gain of this stage is G = -R D gfs. For typical values of R D and gfs the gain of a single JFET common-source stage is in the range 5-20, much less than the maximum gain possible with a bipolar common emitter stage. Both the gain of this stage and the quiescent voltages suffer from wide process variations. These variations can be reduced by adding a resistor to the source like we did for the bipolar version, and sometimes this is done in practice, but not always, because the gain will then be even smaller. Process variations of gain due to variations of gfs are often dealt with in practical circuits by including the stage in a feedback loop. Then variations of gfs cause variations in the loop gain, but not in the closed loop gain. For more info about JFET biasing and the effects of process variations, see Application Note AN102 JFET Biasing Techniques from Vishay/Siliconix (linked at our course web site). V DD R D D V out V in G S Figure 8.2 Common Source Amplifier Stage The input resistance of this stage is essentially infinite (something like Ω) and the input capacitance is around 10 pf. The output impedance is equal to the drain resistance R D, typically a few thousand Ohms. Compared to the bipolar version, the JFET common-source stage has much higher input impedance, lower gain, and comparable output impedance. We did not discuss the noise of the bipolar common-emitter stage, but it s worth knowing that the JFET common-source stage has much lower noise than a typical BJT or MOSFET stage when the signal source impedance is above about 10 kω. 8.5

6 Pre-Lab Problems 1. Consider the common-source amplifier circuit of Fig Suppose you build this circuit with the JFET used to generate the output characteristics shown in the 2N4416A data sheet, lower right plot on page 7.3. If we use V DD = 15V, and we want V DS = 3 V at V GS = 0, (A) what value of R D should we use? (B) What will the value of I D be? If V DD =10V, what will I D be in this case? 2. Find the small-signal voltage gain of the common-source stage you designed in Problem 1 for both V DD values (10V and 15V). Find any quantities you need from the lower right plot on page 7.3 of the data sheet (do not use typical values given in the tables). Think carefully how you will find δi D /δv GS. 3. (A) Assume for now that the output impedance of the common-source amplifier of Fig. 8.2 is R out = R D. If the initial output voltage is V out,initial, what size load resistor R L (i.e. connected between the output and ground) must one add in order to cause the output voltage to be reduced to half its initial value (V out,initial /2)? Motivate your reasoning with a circuit diagram to receive any credit. For this circuit diagram, one may treat the amplifier as a black box with input impedance R in, gain G, and output impedance R out = R D. (Remember the Thevenin theorems?) (B) Assume that R in = Ohms. With no load attached, what size resistor would one have to add in series with V in in order to cause the output voltage to be reduced to have its initial value (i.e. V out,initial /2)? Again, motivate your explanation with a circuit diagram to receive any credit. (C) As in 3(B) above, assume that R in = Ohms but you also know that the input capacitance is ~3 pf at 1 MHz for V DS =3V. Considering this capacitance as well, what resistor would one have to add in series with V in in order to cause the output voltage to be reduced to V out,initial /2 when your input signal is a 1 MHz sine-wave? Again, motivate your explanation with a circuit diagram to receive any credit. 8.6

7 Experiment JFET OUTPUT CHARACTERISTICS Use the same 2N4416A JFET for all of your experiments this week! (If you d break it you would have to redo your characterization due to the large process variations for these parts.) Find the pinout diagram on the data sheet, and build the circuit shown in Fig. 8.1b. (The lead marked C on the pin-out diagram is connected to the case. Leave it unconnected for now.) You can use one of your power supply outputs for the variable 0 to +15V drain to source voltage and the other one for the variable 0 to - 5V gate to source voltage. (Warning: Do not apply a voltage outside the range of 0 to -10V between the gate and source.) You could use your DMM to measure the drain current and measure the gate voltage using an oscilloscope. As always, make sure the oscilloscope displays a large enough vertical range to avoid large errors in the voltage reading. 1. Make plots of output characteristics (i.e. plot V DS vs. I D for different values of V GS ) similar to those shown in the data sheet (bottom of 7-3, top of 7-4) for V GS = 0, V GS = 0.1 V, and one other value of V GS. Vary V DS from 0 to +15V. Each plot should have at least 4 points except for the plot for V GS = 0, for that plot make sure that you have at least 10 points in the range of 4-8 Volts. (NOTE: As your transistor heats up due to the power you dissipate in it, the characteristics will change. You can avoid this by applying the V DS voltage for very brief intervals and then read the current right after the voltage turns on. How to do that? Be creative!) 2. (A) Measure the values of V GS(off) and I DSS for your device. V GS(off) is the value of V GS where I D drops to zero. I DSS is the value of I D at V GS = 0 V. (B) Find g fs values for your device at V GS = 0 and for V DS = +3V and +15V using the graphs from problem 1. (C) Based on the values measured in 2A and 2B, does your device meet the specs given on page 7.2 of the data sheet? COMMON-SOURCE AMPLIFER Construct the common-source amplifier shown in Fig Keep all leads as short as possible and add a blocking capacitor between V DD and ground, close to your transistor to avoid parasitic oscillations. The gain bandwidth product of these JFETs is very large. 3. (A) Compute, using your characteristic curves, the value of R D that will give V DS = +3V at V GS = 0 at V DD =15V, and also predict the small-signal voltage gain G. Find a metal-film resistor close to your desired value of R D (or use several in series or in parallel) and measure the resulting quiescent voltage V DS with the gate grounded. 8.7

8 (B) Is the value of V DS you observe consistent with your measured characteristics? 4. (A) Measure the small-signal gain G of your common-source stage at 1 khz. (B) Do you get the value you predicted? If your measured gain is too small, consider the effects of the output resistance R O of the JFET, which is the inverse of the slope of the I D versus V DS curve at the operating point. Remember that the simple gain formula we have been using (G = -R D gfs) is only exact in the limit R O >> R D. Is this a good approximation for your circuit? (C) To avoid making this approximation, replace R D in the gain formula with the parallel combination of R D and R O and recalculate g fs. In order to get and approximate value for R O find the value of V DS in your circuit and use the data from section 1 with V GS = 0. Is the new answer better? 5. (A) Apply a small 100 Hz sine-wave to the input of your amplifier and measure the amplitude V out. Now Place a 1 MOhm resistor in series with the input, and record any change in V out. What does the result imply about the input impedance of the amplifier? How does the input impedance compare to that of the BJT common-emitter amplifier you built last week? How does it compare to the input impedance of a non-inverting op-amp amplifier? Of an inverting op-amp amplifier? Of your scope? Of your DMM? How would that change if you repeat the same measurement at 1MHz instead of 100Hz? Explain what s going on. (B) Connect a load resistor with magnitude equal to 5 R D between V out and ground. Record any changes in V out. From this result, calculate the output impedance R out of the amplifier. Compare the result to the assumption that the output impedance R out is the parallel combination of R D and R 0. How does the output impedance compare to that of the BJT common-emitter amplifier you built last week? Of the output impedance of the op-amp circuits you built? Of the synthesizer you use have used to apply signals to your circuits? 8.8