6. Field-Effect Transistor

Transcription

1 6. Outline: Introduction to three types of FET: JFET MOSFET & CMOS MESFET Constructions, Characteristics & Transfer curves of: JFET & MOSFET

2 Introduction The field-effect transistor (FET) is a threeterminal device used for a variety of applications that match, to a large extent, those of the BJTs. The primary difference between the two types of transistor is the fact that: The BJT is a current-controlled device, whereas the FET is a voltage-controlled device.

3 For BJT, the I C is a direct function of I B ; For FET, I D will be a function of the V GS. In both cases, output current is controlled by an input parameter. The term field effect: For the FET, an electric field is established by the charges present, which controls the conduction path of the output circuit without direct contact between the controlling and controlled quantities.

4 The BJT is a bipolar device, which means that the conduction level is a function of two charge carriers, electrons & holes. The FET is a unipolar device, depending solely on either electrons or holes. One of the most important characteristics of the FET is its high input impedance. Typical A v of BJT is much greater than that of FET.

5 FETs are more temperature stable than BJTs, and smaller than BJTs, making them particularly useful in integratedcircuit (IC) chips. Three types of FETs are presented here: Junction, JFET Metal Oxide Semiconductor Field-Effect Transistor, MOSFET Metal Semiconductor Field-Effect Transistor, MESFET

6 For JFET: They are simply divided into n-channel and p-channel JFETs, of which the charge carries are electrons and holes respectively. For MOSFET: The category is further broken down into depletion and enhancement type, with each has n-channel and p-channel types.

7 Due to its thermal stability & other general characteristics, MOSFET is widely used in computer & DSP fields. Furthermore, by using both n-channel and p-channel MOSFETs together, a new type of FET, Complementary MOSFET (CMOS) is created. It has high input impedance, fast switching speeds and low power consumption.

8 CMOS logic design is now a new discipline. And modern digital logic devices, like DSP processors, micro-controllers and FPGAs, are all made of CMOS materials. For MESFET: It is a more recent development and takes full advantage of the high-speed property of GaAs for RF and computer design. However, it is relatively expensive.

9 Figure: Difference between BJT & FET

10 Construction of JFETs The JFET is a three-terminal device with one terminal capable of controlling the current between the other two. The n-channel device will be the prominent device, just like npn transistor in the discussion of BJT. For p-channel device, the result will be obtained by changing the signs of some parameters.

11 The basic construction of n-channel JFET is shown in the figure. The major part of the structure is the n- type of material, which forms the channel between the embedded layer of p-type material. The top of the n-type of material is connected to a terminal called drain (D), whereas the lower end called source (S).

12 The two p-type of material are connected together and to the gate (G) terminal. So the JFET has two p-n junctions under no-bias conditions. And a depletion region is generated at each junction with no free carrier. Also illustrated in the figure, it is the water analogy.

13 The water pressure can be likened to the applied voltage from drain to source (inside the JFET), which establishes a flow of water (electrons) from the spigot (source). For FET, the gate through an applied potential, controls the flow of current to the drain. The terminology, (D, G & S), is defined for electron flow.

14 Figure: JFET Construction

15 Biasing: V GS = 0, V DS > 0 As shown in the figure, a positive voltage V DS ( =V DD )is applied across the channel. The gate is connected directly to the source to establish the condition V GS = 0. The electrons are drawn to the drain, leading to the current I D, which is also the same as I S. And the I D is solely limited by the resistance of the n-channel between D & S.

16 The depletion region is wider near the top of both p-type materials. The reason is that upper region is more reverse-biased than the lower part, thus a wider depletion region. Also, the p-n junction is reverse-biased for the whole length of the channel, leading to no current in the gate terminal. I G = 0 is an important characteristic of JFET.

17 When V DS increasing, I D will also increase. As V DS increases, the depletion regions will widen, causing reduction in the channel width and a higher resistance. If V DS is increased to a level V P, where it appear that the two depletion regions would touch, a condition referred to as pinch-off will result.

18 The level of V DS that causes pinch-off condition is called pinch-off voltage, denoted by V P. Actually, under pinch-off condition, the current I D maintains a saturation level, defined as I DSS. I DSS is the maximum drain current for a JFET and is defined by the conditions V GS =0 and V DS > V P.

19 Figure: Biasing of JFET (V GS = 0, V DS > 0)

20 Figure: I D versus V DS for V GS = 0

21 Biasing: V GS < 0 For BJT, the characteristics is plotted to show the relationship between I C and V CE for different levels of I B. For FET, the characteristics is drawn to show the relationship between I D and V DS for various levels of V GS. The V GS is the controlling voltage of JFET, just like I B for the BJT.

22 For the n-channel device, V GS is made more and more negative from its V GS = 0 level. The saturation level of I D has been reduced as V GS is made more and more negative. Eventually, when V GS = -V P, it is sufficiently negative to establish a saturation level that is zero.

23 For all practical purpose, the device has been turned off. The V GS that results in I D = 0 is defined by V GS = V P, with V P being a negative voltage for n-channel and a positive voltage for p- channel JFETs. The region to the right of the pinch-off locus is employed in linear amplifier and referred to as linear amplification region.

24 Figure: Biasing of JFET (V GS < 0)

25 Figure: JFET characteristics (V GS < 0)

26 Symbols of JFET The graphic symbols for the n-channel and p-channel JFETs are shown in the figure. Note that the arrow is pointing in for the n- channel device. This means that I G would flow if the p-n junction were forward-biased. For p-channel device, the only difference in the symbol is the direction of the arrow.

27 Figure: Symbols of JFET

28 Transfer Characteristics For BJT, the output current I C and input controlling current I B are related by constant, which is in the following equation form, I C = f(i B ) = I B For JFET, the relationship between the output and input quantities is not as simple as the that of BJT.

29 The relationship between the I D output and V GS is defined by Shockley s equation: I D I DSS V 1 GS VP where the I DSS and V P are constants, and V GS controls the I D. The squared term results in a nonlinear relationship between the I D output and V GS. 2

30 The transfer characteristics are properties of JFET itself and are unaffected by the network in which the device is used. Obviously, the transfer characteristics can be obtained by Shockley s equation. It can also be obtained from the output drain characteristics. We draw both curves with a common vertical scaling.

31 One is a plot of I D versus V DS, whereas the other is I D versus V GS. Using the drain characteristics on the right of the vertical axis, we can draw a horizontal line from the saturation region of the curve to the I D axis. The result current level for both graphs is I DSS.

32 The point of intersection on the I D versus V GS curve will be as shown since the vertical axis is defined as V GS = 0. If a horizontal line is drawn from the V GS = -1V curve to the I D axis and then extended to the other axis, another point on the transfer curve can be located. Continuing with V GS = -2V, -3V and V P (- 4V), we can complete the transfer curve.

33 The transfer characteristics are a plot of an output current I D versus an inputcontrolling quantity, V GS. It s a direct transfer from input to output variable. The non-linearity of the curve is obvious from the different space between curves of different V GS level, also from the curves themselves. It is the transfer curve of I D versus V GS that will receive extended use in the analysis of Chapter 7.

34 Shorthand Method The transfer curves are useful and there are ways to plot it. By Shockley s equation, it s precise but the calculation is time-consuming. By the drain characteristics, it s not easy since the drain characteristics should be known first. Here, a shorthand method will plot the curve in a efficient manner while maintaining an acceptable degree of accuracy.

35 The basic concept of the shorthand method is that the curve is sketched out with only several key points which are easy to obtain. First, from Shockley s equation V 1 GS I D I DSS VP If V GS = 0.5V P, then I D I DSS V / 2 1 P VP I DSS

36 If I D = 0.5I DSS, then 0 V.5 1 GS I DSS I DSS VP So we get V GS 0.3V P. If V GS = V P, then I D = 0. If V GS = 0, then I D = I DSS. So the transfer curve can be sketched to a satisfactory level of accuracy. 2

37 Figure: Transfer curve by shorthand method

38 p-channel JFET For p-channel devices, Shockley s equation can still be applied exactly as it appears. In this case, both V GS and V P will be positive. The transfer characteristics will be the mirror image of the transfer curve obtained with an n-channel and the same limiting values.

39 Figure: Transfer curve of p-channel JFET

40 Summary of JFET Important equations of JFET are as following: I D I V 1 GS VP I D = I S DSS I G 0 And the condition I G 0 is often the starting point for the analysis of a JFET configuration. 2

41 MOSFET: Depletion-Type The basic construction of n-channel depletiontype MOSFET is shown in the figure. A slab of p-type material forms substrate. The S & D are connected through metallic contacts to n-doped regions linked by an n- channel. The G is also connected to a metal contact, but insulated from the n-channel by a silicon dioxide (SiO 2 ) layer.

42 It is this layer of SiO 2 that accounts for I G = 0 and the desirable high input impedance of the device. Some devices provide an additional terminal labeled SS. But in most cases, the substrate and source are connected. From the above, the reason for the name of Metal Oxide Semiconductor FET is clear.

43 Figure: n-channel depletion-type MOSFET

44 Transfer Characteristics Shown in the figure, it is the configuration of n-channel depletion-type MOSFET. The substrate and source are connected as a three-terminal device. A positive potential is applied to V DS. An adjustable potential is applied to V GS. When V GS < 0, the transfer curve is like that of n-channel JFET.

45 When V GS > 0, the drain current I D will increase at a rapid rate. So the positive V GS has enhanced the level of I D and leads to the enhancement region. The region to the left of the vertical axis is the depletion region. The Shockley s equation is still be applicable for the depletion-type MOSFET.

46 Figure: Configuration of n-channel depletion-type MOSFET

47 For the plot of the transfer characteristics of an n-channel depletion-type MOSFET by shorthand method, please see Example 6.3. Shown in the figure, it s the transfer curve of the p-channel depletion-type MOSFET. It is exactly the opposite of that of n-channel. The V GS is positive for most of time and can also be negative. And when V GS = 0, I D = I DSS.

48 Symbols of Depletion-Type MOSFET The graphic symbols for the n-channel and p-channel depletion-type MOSFET are shown in the figure. The D & S is connected by channel through the vertical line in the symbol. The lack of a direct connection between G and channel is shown. The substrate is connected internally as a 3- terminal device.

49 Figure: Symbols of depletion-type MOSFET

50 MOSFET: Enhancement-Type Shown in the figure is the basic construction of n-channel enhancement-type MOSFET. A slab of p-type material forms substrate. The S & D are connected through metallic contacts to n-doped regions. The silicon dioxide (SiO 2 ) layer is still present to isolate the gate platform from the region between D & S.

51 Note the absence of a channel between the two n-doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs. The characteristics of the enhancementtype MOSFET are quite different from anything obtained thus far. The transfer curve is NOT defined by Shockley s equation.

52 Figure: n-channel enhancement-type MOSFET

53 Transfer Characteristics Shown in the figure, it is the configuration of n-channel enhancement-type MOSFET. The substrate and source are connected as a three-terminal device. A positive potential is applied to V DS. When V GS = 0, the absence of an n-channel will result in a zero current.

54 As V GS increases in magnitude, an induced n-type region is formed near the SiO 2 layer. This leads to a measurable current flow between D & S. The level of V GS that results in the significant increase in drain current I D is called the threshold voltage, V T. The channel is enhanced by V GS > 0. This is the reason to the name of this type of MOSFET.

55 If we hold V GS constant and increase V DS, the I D will eventually reach a saturation level. This is the result of the narrower channel at the drain end of the induced channel. The drain characteristics is shown in the figure. For a fixed value of V T, the higher level of V GS, the greater is the saturation level for V DS.

56 For V GS less than V T, I D = 0. It is noticeable that the spacing between the level of V GS increases as the magnitude of V GS increases. This shows the nonlinear relationship between I D and V GS. Actually, I D = k (V GS V T ) 2 where k is a constant and can be obtained through V GS(on) and I D(on) from datasheet.

57 Furthermore, transfer curve can be obtained by setting it side by side with drain characteristics. If a horizontal line is drawn from the V GS = +8V curve to the I D axis and then extended to the other axis, a point on the transfer curve can be located. Continuing with other voltages of V GS, the transfer curve is obtained.

58 It must be remembered that I D is zero for V GS V T. Also, the transfer curve is totally in the positive V GS region and does not rise until V GS = V T. As to how to plot the transfer curve given k and V T for a particular MOSFET, see Figure 6.37 on page 330.

59 Figure: Channel formation in the n-channel enhancement-type MOSFET

60 Figure: Drain & transfer characteristics for n-channel enhancement-type MOSFET

61 p-channel Enhancement-Type MOSFET The construction of p-channel enhancementtype MOSFET is exactly the reverse of that of n-channel one. A slab of n-type material forms substrate. Those p-doped regions are under the drain and source connections. All the voltage polarities and current directions are reversed.

62 The drain characteristics of p-channel enhancement-type MOSFET is shown in the figure. The I D is increasing from increasingly negative values of V GS. Also, I D is zero while V GS < V T. The equation of I D discussed before is also applicable to p-channel devices.

63 Symbols of Enhancement-Type MOSFET The graphic symbols for the n-channel and p-channel enhancement-type MOSFET are shown in the figure. The dashed line between D & S reflects that a channel does not exist. The direction of arrow shows the channel type of the device. The substrate is connected internally as a 3- terminal device.

64 Figure: Symbols of enhancement-type MOSFET

65 Summary of Chapter 6 Introduction to FET For JFET & MOSFET Output characteristics: I D ~V DS Transfer curves: I D ~V GS Shorthand method to sketch transfer curves Graphical symbols