Learning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES

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Silvester Hicks
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1 Learning Outcomes Spiral 26 Semiconductor Material MOS Theory I underst why a diode conducts current under forward bias but does not under reverse bias I underst the three modes of operation of a MOS transistor the conditions associated with each mode I can analyze circuits containing MOS transistors to find current voltage values by first determining the mode of operation then applying the appropriate equations Current, Voltage, & Resistors Kirchoff's Current Law Sum of current a node is equal to current coming a node Kirchoff's Voltage Law Sum of voltages around a loop is Ohm's Law (only applies to resistors or devices that "act" like a resistor) I = or Note: For a resistor, current voltage are related with R as the slope DIODES

2 Semiconductor Material Semiconductor material is not a great conductor material in its pure form Small amount of free charge Can be implanted ( doped ) with other elements (e.g. boron or arsenic) to be more conductive Increases the amount of free charge Pure Silicon PType Silicon (Doped with boron) Electron acceptors NType Silicon (Doped with arsenic) Electron donors 26.5 Transistor Types Bipolar Junction Transistors (BJT) npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter collector However the fact that it requires a current into the base means it burns power (P = I*V) thus limits how many we can integrate on a chip (i.e. density) Metal Oide Semiconductor Field Effect Transistors nmos pmos MOSFETS Voltage applied to insulated gate controls current between source drain Gate input requires no constant current thus low power! We will focus on MOSFET in this class emitter 26.6 ptype ntype ptype base conductive polysilicon ptype collector npn BJT Ntype MOSFET ntype PN Junction Diode 26.7 The PN Junction 26.8 Our understing of how a transistor works will start by analyzing a simpler device: a diode A diode can be formed by simply butting up some p type ntype material together ptype Physical view ntype Anode Schematic symbol of a diode Cathode When we join the two substances the free electrons at the junction will combine with the nearby free holes in a "loose" bond This has two effects: Around the junction there are free charges (they've all combined) creating a Now remember the dopants in n ptype material are still charged (same # of protons/electrons). So this migration has actually created ions thus an ( thus voltage) in the opposite direction ptype ntype

3 Depletion Region Forward Bias Depletion region has free or mobile charge A small is induced due to this recombination Ntype material LOST an electron leaving a ion PType material LOST a hole (GAINED an electron) leaving a ion The voltage is in the opposite direction Now let's place an eternal positive voltage source across the diode Holes electrons are pushed toward each other reduce the depletion region If the eternal voltage is high enough the charges will have enough to overcome the gap start through the diode The positive eternal voltage needed to overcome the depletion region is known as the Voltage V D ptype ntype p n Depletion Region Human convention of current as positive charge flow ptype Depletion Region ntype Physical reality of electron flow Reverse Bias Now let's place an eternal negative voltage source across the diode Holes electrons are attracted to the voltage source terminal (pulled away from the depletion area making the depletion area ep) current is flowing across the junction because both holes electrons are attracted in opposite directions ptype V D ntype Ideal Diode A perfect diode would ideally allow current to flow in It would therefore be a perfect conductor in one direction (forward bias) a perfect insulator in the other direction (reverse bias) Eample: Determine the value of ID if a) VA = 5 volts (forward bias) b) VD = 5 volts (reverse bias) Ideal model: a) I D = = = 100 ma b) Diode is in reverse bias is acting like a perfect insulator, therefore no current can flow I D = More realistic: a) I D = /R S = 86 ma b) I D = 0 V A _ R S = 50 Ω I D Depletion Region

4 Carrier Concentration Even silicon has some amount of free electrons (n) holes (p) We refer to this as the concentration Note: n = p since a free electron leaves a hole behind When we add dopants we change the carrier concentration N A N D is the concentration of respectively Note: N A >> p N D >> n TRANSISTORS Pure Silicon PType Silicon (Doped with boron) NType Silicon (Doped with arsenic) Electron acceptors Electron donors Doped Valence Conduction Bs Impurity atoms, i.e., donors or acceptors replace some silicon atoms in the crystal lattice Donors: a valence of five e.g., phosphorus (P) or arsenic (As)) Acceptors: a valence of three, e.g., boron (B)) Remember these are electrically neutral (same # of protons/electrons), but are easily induced to donate or accept an electron under certain circumstances (i.e. under a voltage) If the donors or acceptors get ionized, each donor delivers an electron to the conduction b. Also each acceptor will capture an electron from valence b leaving a hole behind Normally, at room temperature all donors (density N D ) acceptors (concentration N A ) are ionized A FEW QUICK NOTES 15

5 Body Terminal Recall a PN junction acts like a diode allows current flow when V pn > V thresh We don't want that current flow so we must always maintain appropriate voltage to keep the "intrinsic" diodes in Always keep the Ptype area at a voltage than the Ntype For NMOS: Keep Body = ; For PMOS: Keep Body = We will often not show the body connection assume it is appropriately connected Input ptype Body/Substrate Output ntype Input ntype Body/Substrate P N Input ptype Conventions Since the source is always at the lowest voltage (for NMOS) highest voltage (for PMOS) we generally define all voltages w.r.t. V S Conventionally all terminal voltages are defined wrt V S We also often draw our schematic symbols w/o showing the body terminal NMOS PMOS Vdd 18 or Since MOSFETs are symmetric, which terminal is the source which is the drain? It! For NMOS: is terminal connected to voltage For PMOS: is terminal connected to voltage Input ptype Body/Substrate Output ntype Input ntype Body/Substrate Vdd Input ptype THE BASIC IDEA OF MOS OPERATION NMOS PMOS

6 NMOS vs. PMOS We will do all our analysis for NMOS but all the analogs hold true for PMOS (same equations but different constants flipped n/p, etc.) Note: There are a LOT of equations we can will show HOWEVER we will show you the main equations for the 3 different operating modes of a MOS transistor right now most of the equations thereafter are just support for those primary ones do not need to be memorized, etc Piecewise Functions How would I describe a function that has the following graph? With function for the 3 regions of operation MOS transistors behave differently for 3 given input conditions, so we will describe those 3 cases with f() = NMOS Transistor Physics MOS Modes of Operation Key idea: MOS operation relies on a voltage being developed in two V DS From gate to source in the dimension From drain to source in the y dimension V GS Body ptype y ntype Transistor is off (drain to source is open circuit) (Vt is whatever threshold voltage is needed to turn the transitor on let's say V) Transistor is on drain to source can be modeled as a relationship between voltage/current Transistor is on drain to source allows a of current despite voltage

7 NMOS Cutoff NMOS Depletion If, then holes (p) accumulate at the surface preventing a channel from forming As Vgs increases but is still Vt, some electrons are induced into the beneath the gate creating a region (still no current can flow) but we are getting closer V DS V GS <= 0 Body ptype y ntype V DS 0 < V GS < Vt Body ptype y ntype NMOS Inversion As Vgs increases reaches ( increases beyond), enough electrons are induced into the channel We assume V DS is so there is no horizontal field to create a current flow across the channel, but the channel has now formed NMOS Linear Mode So we have a conductive channel: Now we increase > 0 so current starts to flow The more we increase V DS we get a increase in the amount of current we can induce to flow Wait! If I gave you a black bo showed that current through it grew linearly with voltage across it then We can treat the black bo like a! i i V? V DS = 0 V GS > Vt Body ptype y ntype Conductive channel (The voltage all along the actual channel is appro. V GS Vt) V DS > 0 V GS > Vt V s = 0 Body ptype V D > 0 ntype Conductive y channel V i = mv Let m =

8 NMOS Linear Mode NMOS Saturation What happens as we continue to increase V DS? Notice the shape of the channel. It is near the drain? Why? Because so there is more pull upward on the electrons near the drain than at the source As we increase V DS the channel gets more more narrow near the drain until it actually. V DS > 0 V GS > Vt V s = 0 Body ptype V D > 0 ntype Conductive y channel In linear region: Vgs > Vt 0 < Vds < VgsVt (Vds => Ids ) In saturation region: Vgs > Vt Vds > VgsVt (Vds => Ids = const) E ver > 0 E hor > 0 30 NMOS Saturation Once the channel starts to pinch off At this point an increase in V DS (i.e. stronger electric field) does NOT induce The etra energy being applied is used to simply get the electrons across the depletion zone between the pinched off channel the drain And as we increase V DS the channel pinches off even more meaning we have use more energy to get electrons across Analogy: You can carry 15 items from one place to another in 10 minutes. I come to you say, I'll give you a helper (increase V DS ) but you have to transport 30 items (i.e. it becomes more work/harder). Does the rate of transfer change? No, your additional help/energy is on the additional you have to perform. V DS > 0 V GS > Vt V s = 0 Body ptype V D > 0 ntype Conductive y channel nmos Crosssectional View Summary Operating in the linear region Another way to think about it: Vgs > Vgd so the channel is deeper near the source than the drain, but a continuous channel does eist Operating at the edge of saturation V DSAT = Voltage where we crossed from linear (resistive) mode to saturation mode = Voltage at the pinchoff point = This is the voltage at which electrons in the channel are pulled into the drain by Vds rather than staying at the surface due to Vgs Operating beyond saturation Any increase in V D beyond V DSAT is dropped across the depletion region from drain to the pinchoff point causing the channel to eperience the same voltage V DSAT on one side thus the same 32 amount of current to flow through the channel

9 Summary of MOS Transistor Modes MOS transistor (Ids/Vds relationship) can be modeled differently based on different operating conditions Open circuit (off) As a simple resistor between & As a constant current source between & Note: (K' = K N for nmos, K P for pmos) Mode Condition Ids, Vds Relationship Off 0 Resistive Saturation Getting More Current to Flow Note: I ds is proportional to K' (K N or K P ) AND the ratio of For a transistor is some intrinsic (we can't change it) measurement of how well the transistor we built will conduct [Note:! ] As a designer we can change W L W _ = Conductivity _ ; L _ = Conductivity _ As circuit designers, we can: We can easily choose Hard to change ptype Input Output W ntype L Mode Condition Ids, Vds Relationship Resistive Saturation Changing is something we will do a lot of in digital designs, mainly to influence of a gate nmos I D as a Function of V DS V GS PMOS Operation Threshold voltage is now negative (e.g. 0.7V) The gate has to be at a low enough voltage compared to the body to repel the electrons attract free holes to create a conductive channel of holes In cutoff: Vgs > Vt In linear region: I D vs V GS for V DS > V DSAT V D V G Input ntype Body/Substrate Vdd Input ptype Vgs Vt VgsVt < Vds < 0 In saturation region: Vgs Vt Vds < VgsVt 35 PMOS

10 IV Characteristics Vdsp just means the drain is at a lower voltage than the source in the PMOS Idsp just means the current is actually flowing from source to drain in the PMOS V gsn5 V gsp1 V gsp2 V gsp3 V gsp4 V gsp5 V DD V dsp I dsn 0 I dsp V dsn V DD V gsn4 V gsn3 V gsn2 V gsn Summary of NMOS or PMOS Transistors So that we don't get too caught up in the negative signs of PMOS transistors let us use the absolute value (ignore direction of current flow sign of voltage) to arrive at one set of equations for either type We assume though: NMOS: Vgs, Vt, Vds are all current flows from D to S PMOS: Vgs, Vt, Vds are all current flows from S to D Mode Condition Ids, Vds Relationship Off 0 Resistive Saturation Eample NMOS Region Calculation V t of an NMOS transistors is 0.35 v V DD = 1.2v What are the conditions for the transistor to be ON Output ( ) EXAMPLE DERIVATIONS In Linear region Controlling Input (Gate) In saturation region 40

11 Eample PMOS Region Calculation V t of a PMOS transistors is 0.35 v V DD = 1.2v What are the conditions for the transistor to be ON In Linear region In saturation region Controlling Input (Gate) Output () Eample Current Calculation A 0.6 µm process from AMI semiconductor t o = 100 angstroms (1 angstrom = 1E10 m = 1E8 cm) ε o =3.9*8.85E14 F/cm µ = 350 cm 2 /V.s V t = 0.7 V Plot I ds vs V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4λ/2λ I ds (ma) V gs = 2 V 0 gs = V ds V gs = 5 V gs = 4 V gs = A/ V L L L 14 W W W o 8 β = µ C = ( ) = µ Calculate Vout Calculate Vout Given V T = 0.5, V DD = V GS = 3V, K N = 240 μa/v 2, W/L = 1, R L = 10KΩ Note: Vout = V DS thus V L = V DD V DS Consider what mode the transistor is in, then setup a KCL equation at the output We know V GS V T is 2.5 while VDS (=Vout) is very likely lessthan 2.5 since we have a voltage divider R L = 10K with most of the 3V dropped across R L leaving Vout to be small Thus we are in mode Given V T = 0.5, V DD = V GS = 3V, K N = 240 μa/v 2, W/L = 1, R L = 10KΩ Note: Vout = V DS thus V L = V DD V DS Finish solving the previous problem then consider the change in the answer if the Width of the transistor is doubled $% &' Mode Condition Ids, Vds Relationship Resistive Saturation Mode Condition Ids, Vds Relationship Resistive Saturation

12 26.45 Recall the Inverter General problem: Given Vin other parameters calculate Vout Take a moment think: What should the plot of Vin vs. Vout look like How can we calculate Vout, given Vin? Calculating "DC" (Constant) Voltage Input/Output Relationship STATIC INVERTER ANALYSIS Ideal (CMOS comes close) Other Implementations may be nonideal Step 1: Setup a KCL Equation Calculating the static ('steady state') Vin/Vout relationship? Use equations for MOS transistors by recognizing the following: according to KCL I LOAD = 0 (net gate = no current flow) So The current through the PMOS must equal the current through the NMOS (we can set them equal) we have equations for the currents ( I DS,P I DS,N ) Step 2: Use Educated Guess for Modes of Operation But what mode are they in? V GS,N = V DS,N = V GS,P = Given the assumptions V T,N = V T,P = 0.5V; Vdd = 3.0V; k n = 2k p ; L=1; W n = 1; W p = 2; Vin = 0.8V Then use the Vin/Vout relationship the given value of Vin to make an educated guess Since Vin is low, Vout should be V GS,N Vt = V DS,N = close to Vdd NMOS is in V GS,P V T = while V DS,P = 3V = PMOS is in 1. Because Vin = 0.8V Vout must be

13 26.49 Step 3: Setup Eqn & Solve for Vout Use the current equations for each transistor in its appropriate mode solve for Vout,),* 1 2, 2,),),),),,' 1 2,,., / 2. *,),),),) =., / 2 * =. 2 / *,, = = 0.09 continue on to solve for Vout / * 0 0.5

UNIT 3: FIELD EFFECT TRANSISTORS

FIELD EFFECT TRANSISTOR: UNIT 3: FIELD EFFECT TRANSISTORS The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There are