Combinational Logic Gates in CMOS

Transcription

1 Combinational Logic Gates in CMOS References: dapted from: Digital Integrated Circuits: Design Perspective, J. Rabaey UC Principles of CMOS VLSI Design: Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian EE26 Lecture Notes by Prof. K. ult UCL

2 Improved Loads Differential Cascade Voltage Switch Logic (DCVSL)

3 Example

4 Pass Transistor Logic

5 Pass-Transistor Logic Switch Network Reduced number of transistors No static power consumption

6 Pass Transistor Logic Control Signal P Pass Signal V F = Product Term F Z V if if P P

7 asic Pass Transistor Logic Model Control Signals P i Pass Signals V i F = Sum of Products F P ( V ) P 2( V 2) P n( V n )

8 XNOR Gate Truth Table OUT Pass Function Modified Karnaugh Map

9 oolean Function Unit Operation P P2 P3 P4 ND(,) XOR(,) OR(,) NOR(,) NND(,)

10 NMOS-only switch Problem: V does not pull up to, only to - V tn(body-effect) Cannot completely turn off the PMOS transistor Causes static power consumption

11 Solution Transmission Gate

12 Transmission Gate Implementation P P2 F(,) P3 P4 F(,) P P2 P3 - P4

13 Transmission Gate XNOR - - OUT

14 Transmission Gate (Inverting) Multiplexer S S S VDD M2 S F M S GND In S S In 2

15 Transmission Gate XOR

16 Resistance of Transmission Gate is discharged originally For NMOS, V GS = V DS, saturated or cutoff For PMOS, V GS = -, V DS increases from - to, starts out in saturation, then transitions into non-saturation Vout V tp : NMOS saturated, PMOS saturated V tp V out V DD V tn : NMOS saturated, PMOS linear V DD V tn V out : NMOS cutoff, PMOS linear

17 Resistance of Transmission Gate V out

18 pproximations ssume both in linear region, ignore body effect G eq R eq n( V ( V n DD DD V ( V V tn V V tn )( V ) ) ( V p DD V V ) tp ) ( V ssume both in saturated region G eq I n V I DD n( V p DD V tn ) 2 2V ( V DD p DD p DD V V ( V tp ) 2 tp V )( V ) V )

19 When Output Closely follows Input Region : NMOS unsaturated, PMOS off R on pmost nmost Region : NMOS unsaturated, PMOS unsaturated Region C: NMOS off, PMOS unsaturated Transmission gate V in

20 Delay in Transmission Gate Networks Distributed RC network

21 Elmore Delay To solve for actual delay dvi ( t) dt R C eq V i ( t) Vi ( t) 2V i( t) Estimate the dominant time constant: assume all internal nodes are pre-charged to VDD, and a step input is applied N N N C Req R eq C k jk k jk N N n( n ) 2 R eq C

22 Delay Optimization by uffer Insertion Delay of RC chain Delay of buffered chain m t p opt.69.7 t n m R pbuf eq C t p.69 m( m ) 2 n( m ).69 R 2 eq R eq N C n( n ).69 R 2 C n m n m t t pbuf pbuf eq C

23 Transmission Gate Full dder P C i C i P P S Sum Generation P P P C o Carry Generation C i C i Setup C i P

24 dder Truth Table C.(G) + + (P) SUM CRRY SUM = + + C CRRY = C if + = CRRY = (or ) if + =

25 Solution 2 Level Restoring Transistor for NMOS Only Logic Full Swing Disadvantage: More complex, larger capacitance

26 Proper Sizing of Level Restoring Transistor In transient, conducting path from M r to M 3 via M n when is low, switches from low to high, and X is high M r must not be too large, otherwise, X cannot be brought below threshold voltage, V M, of inverter, M r cannot be turned off

27 Pass-Transistors Single Transistor Pass Gate with V T = V 5V V Out 5V WTCH OUT FOR LEKGE CURRENTS

28 Complimentary Pass Transistor Logic Pass-Transistor Network F (a) Inverse Pass-Transistor Network F F= F=+ F=Ý (b) F= F=+ F=Ý ND/NND OR/NOR EXOR/NEXOR

29 4 Input NND in CPL Total number of transistors needed = 4 (including the final buffer) ut ND function is simultaneously present t phl =.5ns, t plh =.45ns

30 Dynamic Logic

31 Dynamic Logic M p Out M e In In 2 In 3 PDN C L In In 2 In 3 PUN Out M e M p C L n network p network 2 phase operation: Precharge Evaluation

32 Example N + 2 transistors Ratioless No static power consumption Small Noise Margins (NM L ) Requires Clock Pull-down resistance increases due to the evaluation transistor

33 Transient Response 6. V out Vout (Volt) EVLUTION PRECHRGE..e+ 2.e-9 4.e-9 6.e-9 t (nsec)

34 Dynamic 4 Input NND Gate Out In In 2 In 3 In 4 GND

35 Reliability Problems Charge Leakage M p Out () (2) C L V out precharge evaluate t M e (a) Leakage sources (b) Effect on waveforms t Dynamic Minimum circuits Clock require Frequency: a minimal > MHz clock rate

36 Charge Sharing (redistribution) case ) if V out < V Tn M p Out C L = C L V out t + C a V Tn V X or M a X C L V out = V out t = C a V C DD V Tn V X L = M b C a case 2) if V out > V Tn M e C b C a V out = C a + C L

37 Minimize Charge Sharing Keep the change in storage voltage below V tp the output might be connected to a static inverter as in Domino logic C C a L V DD V tp V tn.2 C a is normally smaller than C L, but if there is series connection of NMOS transistors, internal capacitances can be strung together and that can increase the voltage change

38 Charge Redistribution - Solutions M p M bl M p M bl Out Out M a M a M b M b M e M e (a) Static bleeder (b) Precharge of internal nodes

39 Clock Feedthrough M p Out could potentially forward bias the diode M a X C L 5V M b C a overshoot M e C b out

40 Clock Feedthrough and Charge Sharing output without redistribution (M a off) feedthrough V (Volt) 6 4 out internal node in PDN t (nsec)

41 Cascading Dynamic Gates V M p Out M p Out2 In In Out V Tn Out2 V M e M e t (a) (b) Only Transitions allowed at inputs!

42 Domino Logic M p Out M p M r Out2 In In 2 PDN In 4 PDN Static Inverter with Level Restorer In 3 M e M e

43 Domino Logic - Characteristics Only non-inverting logic Very fast - Only transitions at input of inverter affects the next Domino Static inverter increases noise immunity, increase the size of PMOS to increase V M Proper sizing of inverter to drive the fan-out in optimal way dd a level-restoring transistor to overcome charge sharing and charge loss

44 np-cmos (Zipper CMOS) M p Out M e In In 2 In 3 PDN In 4 PUN Out2 M e M p Only transitions allowed at inputs of PUN Reduced noise margins: NM H = V tp, NM L = V tn

45 Full dder Circuit C C -carry C -sum C C C

46 np-cmos dder C i2 C i S C i C i C i C i S C i Carry Path

47 Manchester Carry Chain dder.5 Total rea: 225 m 48.6 m P P P 2 P 3 P 4 M M M2 M3 M C i, G G G 2 G 3 G 4 C o,

48 dder Truth Table C.(G) + + (P) SUM CRRY SUM = + + C = P + C CRRY = C if P = CRRY = if P = CRRY = G + PC

49 CMOS Circuit Styles - Summary