On Chip High Speed Interconnects: Trade offs in Passive Compensation

Transcription

1 On Chip High Speed Interconnects: Trade offs in Passive Compensation Term Project: ECE469 High Speed Integrated Electronics Raj Parihar

2 Problem Statement Scaling and Current Scenario Increasing Chip Complexity (More functionality) Local wire % grows exponentially CAD tool should account this increased wire density Global On-Chip Communication Cost Wire performance, relative to gates will continue to worsen Aggressive use of repeaters and buffers results into increased chip area and power consumption Signal Distortion over a serial channel Frequency dependency of attenuation and phase velocity 12/17/2008 Raj Parihar 2

3 Problem Statement High Speed On Chip Interconnects Most on chip wires are open circuit Tx line Tx Zo Rx On Chip Passive Compensation Reduces the reflection by termination Introduces Latency Power Trade off Tx Zo Rx Z t 12/17/2008 Raj Parihar 3

4 Papers Michael P. Flynn and Joshua J. Kang, Global Signaling over Lossy Transmission Lines, IEEE ICCAD 2005 A. Tsuchiya et al, Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects, IEEE CICC 2005 H. Chen, David Harris, Surfliner: A Distortion less Electrical Signaling Scheme for Speed of Light On-Chip Communications IEEE ICCD 2005 Chun-Chen Liu et al, Passive Compensation For High Performance Inter-Chip Communication IEEE ICCD 2007 Yulei Zhang et al, On-Chip Bus Signaling Using Passive Compensation, IEEE EPEP /17/2008 Raj Parihar 4

5 Introduction: On Chip Interconnects Interconnect Propagation Delay > 1/6 Rise Time of Digital Signal Lumped Circuit models are no more valid Interconnects has to be analyzed as Tx line High Speed Transmission Line Attenuation Repeaters/ Signal boosters are required Reflection Proper matching at the receiver end is required ISI is a problem to achieve high speed 12/17/2008 Raj Parihar 5

6 Modeling: On Chip Interconnects R wire C wire Distributed RC Wire Model Simple to understand and analyze Less accurate at higher frequency C wire d Repeater Repeated RC Wire Model Liner Delay w. r. t. length of wire Increased power and die area d R wire L C R L C Lossless Transmission Line High BW; Less power consumption Unrealistic to implement Lossy Transmission Line More realistic and accurate Reflections, Dispersion, Attenuation 12/17/2008 Raj Parihar 6

7 Metrics of Transmission Line Characteristic Impedance: Z o Ratio of voltage to current for forward waves f Z o = V + f = s L Wave Velocity I + C Phase Velocity: Speed of a point ~ Wave s speed Group Velocity: Speed of overall energy Return Loss How much power is reflected? VSWR Voltage Standing Wave Ratio: Ration of V + and V - w 12/17/2008 Raj Parihar 7

8 TL Wave Propagation and Matching Why do we require matching? To make sure the whole power is delivered to load To avoid the source oscillation and noise in link Avoid reflections and attenuation Without Termination V near =V far =V dd With Termination* V near = V dd 2 f V far = V near αl 12/17/2008 Raj Parihar 8

9 Terminations: Most Commonly Used Parallel Termination Zo Removes reflections Dissipates Power R t Pull/ Pull Down Termination Zo Improved Noise Margin Two components to optimize R t AC Termination Zo R t No DC Power Dissipation C is difficult to optimize Cc R s Series Termination Zo Attenuates reflected signals Lowers the voltage swing 12/17/2008 Raj Parihar 9

10 Findings: Thesis Eye Opening (V) Eye Opening (V) Eye Opening VS Bit Rate 1 Open Circuited TL Passively Terminated 0.5 Bit Rate (Gbps) 100 Eye Opening VS Normalized Z 1 Attenuation Constant Alpha = f (R t ) 20 Gbps, L = 10mm Normalized Termination Z 100 Energy/Bit (fj/bit) Output Voltage (V) Energy/Bit VS Impedance 46 Open Circuited TL Passively Terminated Optimally Terminated ( +40%) 28 Terminator s Impedance (Ohm) 1000 Step Response of Lossy TL 1 Long TL Short TL Input Signal 0.5 Time (ns) 5 12/17/2008 Raj Parihar 10

11 Survey: Contemporary Research Work Surflinear Architecture Improvement over Surflinear Z o G n Z o G n R t Emulation of distortion less transmission line Shunt G to compensate the R voltage drop High Speed, High BW, Low Jitter, Low Power Attenuation persists, Many on chip component Mismatch and process variation; G = RC/L Addition of Rt at Rx end to match with load Reflections are reduced by matching at Rx Rt can be chosen to optimize Eye opening Attenuation persists, Many on chip component Mismatch and process variation; G = RC/L Parallel Termination Most Recent: Parallel RC at Rx Z o R t R d Z o 2R L Simple to find the optimum termination R value Reduces the reflections to avoid the oscillation Constant power consumption Termination is sensitive to R process variation C 2R L d Single ended on chip T line to minimize power Series resistance minimizes the reflected wave Implementation of on chip C is area consuming 12/17/2008 Raj Parihar 11

12 Passive Termination and TL: Trade Offs Pros Improved Bandwidth Improved bit rate at high frequency Low rise time thus low latency Cons Increased Power consumption Reduced Noise Margin at low speed Process Variation Inductance Modeling 12/17/2008 Raj Parihar 12

13 Conclusion: Guidelines When on chip termination is required? Optimum termination? Minimum sensitivity to process variation Maximum eye opening in voltage output Desired bandwidth and acceptable power consumption Area VS Power Consumption (R Value) 12/17/2008 Raj Parihar 13

14 Appendix Simulation Results Mismatching, Reflection and VSWR

15 Z o = 50 ohm, Z L = 200 ohm; VSWR = 4 12/17/2008 Raj Parihar 15

16 Z o = 50 ohm, Z L = 50 ohm; VSWR = 1 Matched Case: No Reflected Wave 12/17/2008 Raj Parihar 16

17 Z o = 50 ohm, Z L = 20 ohm; VSWR = /17/2008 Raj Parihar 17