Written Examination on. Wednesday October 17, 2007,

Transcription

1 Written Examination on Wednesday October 17, 2007, The textbook and a calculator are allowed on the examination 1. The following logical function is given Q= AB( CD+ CE) + F a. Draw the schematic using complementary CMOS logic. Do not use more than 12 transistors. (2p) b. Balance the design. Assume that only one conducting path exists. In general a PMOS/NMOS ratio between 3 and 3.5 is practiced to balance circuits. However, in this problem a ratio at 2.5 is required in order to save area. (2p) c. Assume that the n-channel transistor with the input F has the on-resistance. Determine the total resistance from the output Q to GND if all inputs are high. (2p)

2 2. The layout for a logic function is shown in Figure 1. V DD PMOS Q A B B A Q NMOS GND Figure 1. The layout for a logic function a. Draw the transistor chart for the function. (0.5p) b. Draw the Euler paths in the transistor chart. (0.5p) c. What logic family do the circuit belong to. (0.5p) d. Draw the transistor chart for the corresponding dynamic gate (of precharge type). (1p) e. What logic functions Q and Q does the circuit perform? (1p) f. Describe the importance of duality, briefly, in the logic networks of the circuit. (0.5p) g. Describe the parasitic capacitances, of importance, that can be found in the output node Q. (2p)

3 3. Figure 2 shows the I D versus V DS characteristics for an NMOS and PMOS transistor in a 0.25 micron technology. For minimum sized transistors, in the same technology, the following is given: W min = μm, k n = 115 μa/v 2, k p = -30 μa/v 2, V Tn = 0.43 V, V Tp = -0.4 V, λ n = /V, λ p = /V I / I ( μa) D n D p V GS = -2.5 V GS = 2.5 V GS = V GS = V GS = V GS = V GS = V GS = V GS = 1.25 V GS = V GS = V GS = V 2 2 DS-n / V DS-p V DD (V).5 V GS = V GS = Figure 2. Load characteristics for an n- and p-channel transistor a. Find the saturation voltages V DSATn and V DSATp. (1p) b. Determine the equivalent resistance eq-n and eq-p graphically for the two transistors. (1p) c. Determine the widths W n and W p for the two transistors plotted in Figure 2, assuming that a minimum length L min is used. (1p) d. Draw the voltage transfer characteristic (VTC) for an inverter designed with the two transistors, by using values extracted from the graph in Figure 2. (2p) e. Find the threshold point V M, the noise-margin-high NM H, and the noise-margin low NM L, by using values extracted from the graph in Figure 2. (1p) 4. Figure 3 shows an on-chip metal wire network which is driven by a buffer with the driver resistance driver = 500 Ω. Each peace of wire is 1 mm long, the feeding wire is 15 μm wide, and the other wires are 5 μm wide. All the three connecting wires are terminated by

4 a capacitance = 50 ff. The metal has a sheet resistance at 0.1 Ω/square, an area capacitance at 0.04 ff/μm 2, and a fringing capacitance at 0.06 ff/μm. driver Figure 3. An on-chip metal wire network a. Calculate the resistance and the capacitance for the feeding wire and one of the other wires. (1p) b. Assume that we use the lumped model. Determine the propagation delay t p-lumped when all resistances and all capacitances are lumped together as shown in Figure 4a. (1p) driver wires feed 3 driver feed wires C feed 3 Cwires C 3 Cload C feed Cwires (a) (b) (c) c. Assume that the wires are distributed. Derive the propagation delay t p-distrib, according to the model in Figure 4b. (2p) d. Use the Elmore delay model and calculate the propagation delay t p-elmore at one of the ending nodes, according to the model in Figure 4c. (2p)

5 5. Figure 6a and Figure 6b shows the logic diagram for the same logic function. Figure 6c shows the same logic functions, but with two inverters added. Assume the following capacitive values for the nodes: n 1 = 4 ff, n 2 = 1 ff, n 3 = n 4 = n 5 = 2 ff, and n 6 = 4000 ff. The equivalent resistances in the transistors are eq = 10 kω for both n- and p-channel transistors. n 1 n 3 n 2 n 5 n 1 n 6 n 4 (a) (b) (c) Figure 6. Combinational logic circuits realizing a four-input AND function a. Determine the propagation delays t plh and t phl regarding the nodes n 2 and n 5, i.e. four delays shall be determined: t plh-a, t phl-a, t plh-b, and t phl-b. (2p) b. Give a brief advice on how to design, e.g. a four-input AND, regarding the fan-in? (0.5p) c. Assume that the circuit in Figure 6a will have the same load as in Figure 6c, i.e. n 2 = 4000 ff. Determine the propagation delay t plh for that case. (0.5p) d. In Figure 6c, two buffer inverters are added to the original design in Figure 6a. Determine propagation delay t plh and the effective-fan-out f for the inverters, when designed to give the shortest delay. Here, it can be assumed that there are no self loading in the nodes, i.e. the proportionally factor, between the intrinsic and the extrinsic load, γ = 0. (2.5p) e. Give some brief reflections on the delay improvement from 5c to 5d and comment the optimum effective-fan-out f for the shortest possible delay. (0.5p) 6. Hand in the course evaluation at next page. (0p)

6 Evaluation - Digital IC-Design 2007 I am a Civilingenjörsstudent What is your general opinion about: Exchange Student International Master Student The course The book The course homepage What is your opinion about the Lectures/Lecturers: Peter Nilsson Viktor Öwall What is your opinion about the Seminars/Exercises: Johan Löfgren What is your opinion about the laboratory work: Hugo Hedberg Johan Löfgren Stefan Molund What changes do you suggest for next year? Other comments: